Test, and the Cost of Being Sure

Every finished chip is tested, and testing is priced in machine time. That makes the whole subject reducible to one number: how long the part sits on the tester. For AI accelerators that number changed by an order of magnitude. An analyst's account puts a 5nm-class mobile processor at roughly 30 to 60 seconds against a Blackwell-class accelerator at well over 20 minutes.

The economics follow arithmetically. Cost of test as a share of a chip's selling price, historically under 2%, is put at 5 to 7% for leading-edge AI parts — roughly tripled. That is a large number for a step most accounts of semiconductor manufacturing skip, and the pressures raising it do not reverse: more transistors to exercise, 700 to 1,200 watts to handle during the test itself, and more test insertions because the parts are too expensive to ship unproven. Writing the test program for a new part is itself put at 6 to 18 months of engineering work, so capacity cannot be conjured quickly even where machines exist.

Stacking changed what testing is for. In a conventional part a bad die is a bad die. In an HBM stack, a bad die condemns everything bonded to it — a defect found after assembly means the whole package is scrapped, including the good dies and the labour that joined them. So known-good-die testing before stacking became mandatory rather than prudent, which moved the expensive step earlier in the process. The difficulty compounds: stacking DRAM dies directly on one another creates extreme density and heat during test, telling the individual dies apart needs purpose-built equipment, and HBM moves through generations faster than conventional memory — eight-high stacks to twelve, sixteen, even twenty-four.

What a capacity constraint looks like from outside is margin expanding much faster than revenue, and the audited results show exactly that shape. For the year ended 31 March 2026, Advantest's net sales rose 44.7% to 1,128.6 billion yen while operating income rose 118.8% to 499.1 billion — profit growing at roughly two and a half times the rate of sales. The company forecasts a further 25.8% of sales growth. Its own stated explanation is unglamorous: significantly higher sales of SoC test systems, driven by the growing complexity of semiconductors and by demand for HPC and AI parts.

The market is an effective duopoly and it concentrated further. Combined share is put above 90%, with one supplier reported moving from 56% to 66% of the SoC tester market inside twelve months — a ten-point gain in a mature two-horse market, attributed to sitting inside the accelerator supply chain at the moment accelerators became the only part of semiconductors growing quickly. Capacity, not demand, is described as the binding constraint, with production ramping toward 10,000 SoC test systems a year against a previous target of 7,500.

What this page deliberately does not do is compare the two suppliers. One appears here through audited consolidated results; the other's own filings were not retrieved, so no figure for it is asserted at all, even though several were available second-hand. Putting a company's audited numbers beside a summary of a competitor's would be a false comparison dressed as a market overview.

The most useful missing thing is a lead time. Whether test is genuinely a bottleneck rather than merely a fast-growing market would be settled by how long a tester takes to deliver, and the trade reporting that covers that sits behind subscription. This page therefore argues the constraint from margin expansion and a stated capacity ramp, which is weaker evidence, and says so.