{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/semiconductor-test","topic":{"slug":"semiconductor-test","name":"Test, and the Cost of Being Sure","description":"A sourced reference collection on the manufacturing step almost nobody writes about — why an AI accelerator occupies a tester for twenty minutes where a phone chip takes under a minute, why a memory stack must be proven good before it is assembled, and why the arithmetic of test time turned a line item into a queue.","coverage_notes":"Fifteenth packet, and the most undercovered subject in this index: testing is a step most accounts of semiconductor manufacturing omit entirely, and it now costs 5 to 7% of a leading-edge AI chip's price. Eight sources were consulted: three were retrieved and read, and five were surfaced and set aside with a stated reason. The primary is unusually strong for this index — a company's own consolidated financial results prepared under IFRS, dated and filed, with named officers — and it was read by extracting the PDF's text streams directly after the fetcher returned only the encoded container. The two supporting sources are independent analysts on subscription platforms, one built around an interview with a named engineer at the same company, and their figures are attributed to them as estimates rather than presented as disclosures. Where the analyst restates the company's own revenue and margins in converted dollars, this page cites the filing instead. The deliberate omission is Teradyne: the other half of a duopoly the analyst puts above 90% combined share appears here only as a name, because its own filings were not retrieved and no figure for it is asserted — placing one company's audited results beside a second-hand summary of a competitor's would be a false comparison dressed as a market overview. The weakest link in the argument is stated in the primer: whether test is genuinely a bottleneck rather than a fast-growing market would be settled by equipment lead times, the trade reporting on which sits behind subscription and was not retrieved, so the constraint is argued from margin expansion and a stated capacity ramp instead. Named gaps, in order of value: tester lead times; SEMI's equipment billings series, which would give an independent non-vendor measure against which a single supplier's growth could be checked; Advantest's own technical briefing on memory test, which would replace a journalist's interview with the company's own document; Teradyne's filings; and syndicated burn-in market reports, which sit behind purchase, disagree with each other and are used nowhere. Not yet editor-reviewed; every assertion reads as reported.","primer":"Every finished chip is tested, and testing is priced in machine time. That makes the whole subject reducible to one number: how long the part sits on the tester. For AI accelerators that number changed by an order of magnitude. An analyst's account puts a 5nm-class mobile processor at roughly 30 to 60 seconds against a Blackwell-class accelerator at well over 20 minutes.\n\nThe economics follow arithmetically. Cost of test as a share of a chip's selling price, historically under 2%, is put at 5 to 7% for leading-edge AI parts — roughly tripled. That is a large number for a step most accounts of semiconductor manufacturing skip, and the pressures raising it do not reverse: more transistors to exercise, 700 to 1,200 watts to handle during the test itself, and more test insertions because the parts are too expensive to ship unproven. Writing the test program for a new part is itself put at 6 to 18 months of engineering work, so capacity cannot be conjured quickly even where machines exist.\n\nStacking changed what testing is for. In a conventional part a bad die is a bad die. In an HBM stack, a bad die condemns everything bonded to it — a defect found after assembly means the whole package is scrapped, including the good dies and the labour that joined them. So known-good-die testing before stacking became mandatory rather than prudent, which moved the expensive step earlier in the process. The difficulty compounds: stacking DRAM dies directly on one another creates extreme density and heat during test, telling the individual dies apart needs purpose-built equipment, and HBM moves through generations faster than conventional memory — eight-high stacks to twelve, sixteen, even twenty-four.\n\nWhat a capacity constraint looks like from outside is margin expanding much faster than revenue, and the audited results show exactly that shape. For the year ended 31 March 2026, Advantest's net sales rose 44.7% to 1,128.6 billion yen while operating income rose 118.8% to 499.1 billion — profit growing at roughly two and a half times the rate of sales. The company forecasts a further 25.8% of sales growth. Its own stated explanation is unglamorous: significantly higher sales of SoC test systems, driven by the growing complexity of semiconductors and by demand for HPC and AI parts.\n\nThe market is an effective duopoly and it concentrated further. Combined share is put above 90%, with one supplier reported moving from 56% to 66% of the SoC tester market inside twelve months — a ten-point gain in a mature two-horse market, attributed to sitting inside the accelerator supply chain at the moment accelerators became the only part of semiconductors growing quickly. Capacity, not demand, is described as the binding constraint, with production ramping toward 10,000 SoC test systems a year against a previous target of 7,500.\n\nWhat this page deliberately does not do is compare the two suppliers. One appears here through audited consolidated results; the other's own filings were not retrieved, so no figure for it is asserted at all, even though several were available second-hand. Putting a company's audited numbers beside a summary of a competitor's would be a false comparison dressed as a market overview.\n\nThe most useful missing thing is a lead time. Whether test is genuinely a bottleneck rather than merely a fast-growing market would be settled by how long a tester takes to deliver, and the trade reporting that covers that sits behind subscription. This page therefore argues the constraint from margin expansion and a stated capacity ramp, which is weaker evidence, and says so.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":3,"inspected_source_count":3,"consulted_reference_count":19,"blocked_reference_count":3,"set_aside_reference_count":16},"figures":[{"kind":"time-series","title":"How long a chip sits on the tester","caption":"Tester time per part. This single ratio is why test economics changed — everything else on this page follows from it.","sourceNote":"Analyst estimates published May 2026: roughly 30 to 60 seconds for a 5nm-class mobile SoC, and well over 20 minutes for a Blackwell-class AI accelerator. Each bar plots the upper end of the stated range or threshold — 60 seconds and 20 minutes — so the real gap is at least this large and probably larger. These are an independent analyst's figures, not a manufacturer's disclosure.","unit":"Tester time per part, seconds","points":[{"label":"Mobile SoC, 5nm class","value":60,"display":"30–60 s"},{"label":"AI accelerator, Blackwell class","value":1200,"display":">20 min"}]},{"kind":"time-series","title":"One test supplier's sales, as filed","caption":"Advantest net sales by fiscal year, from its own consolidated results. The third bar is the company's forecast, not a result.","sourceNote":"Advantest's FY2025 consolidated financial results of 27 April 2026, prepared under IFRS: net sales of 779.7 billion yen in FY2024 and 1,128.6 billion in FY2025, an increase of 44.7%, with an FY2026 forecast of 1,420.0 billion yen, up 25.8%. Fiscal years end 31 March, so FY2025 ended 31 March 2026.","unit":"Net sales, billions of yen","points":[{"label":"FY2024","value":779.7,"display":"¥779.7bn"},{"label":"FY2025","value":1128.6,"display":"¥1,128.6bn"},{"label":"FY2026 (forecast)","value":1420,"display":"¥1,420.0bn"}]}],"blocked_references":[{"title":"All AI Data Center Interconnects Will Be Optical Within 5 Years","publisher":"Semiconductor Engineering","url":"https://semiengineering.com/all-ai-data-center-interconnects-will-be-optical-within-5-years/","source_type":"journalism","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"Intel Foundry — Advanced Packaging (EMIB, Foveros)","publisher":"Intel","url":"https://www.intel.com/content/www/us/en/foundry/advanced-packaging.html","source_type":"company_website","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"TSMC-SoIC (expected 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