Topicshbm
A curated, evidence-first reference collection on High Bandwidth Memory (HBM): what it is, how it differs from conventional memory, who builds and standardizes it, and the major generational, production, and packaging milestones behind today's AI accelerators.
32 sources sit behind this page — including any that arrive with a concept this page shares with another collection. 19 were retrieved and read in full, and only those can back an assertion. 4 could not be retrieved, and 5 were surfaced and deliberately set aside. Every one of them is named in the register below, with the reason in view. How we source this.
The vocabulary this subject is built from, and what we can show about each.
CoWoS is TSMC's wafer-level packaging technology that places a processor and HBM stacks on a shared silicon interposer, used by customers including NVIDIA; TSMC's chronicle of it starts with a 2011 conference paper and lists named customer products from 2012, with more than 60 tape-outs in production or development as of August 2019.
The HBM base die is the bottom, non-memory die in an HBM stack that manages the memory controller, power delivery, refresh/RAS, and protocol conversion functions for the DRAM dies stacked above it.
HBM stacks DRAM dies vertically over a logic base die using through-silicon vias, then packages the stack beside a processor for higher bandwidth and lower power than conventional off-package memory.
MR-MUF is SK hynix's die-stacking process that injects and hardens a liquid protective underfill between stacked dies in a mass-reflow step, which the company states (without independent benchmark confirmation found in this research) improves warpage control versus film-type underfill.
A silicon interposer is a passive, TSV-based silicon layer placed beneath adjacent logic and HBM dies to provide high-density interconnects between them and the package substrate below.
A TSV is a vertical, etched-and-filled electrical connection through a silicon die that lets stacked dies communicate directly, and is the interconnect technology underlying HBM's DRAM stacks.
What actually happened, in order, with sources.
Where this topic’s events took place, as far as our sources establish it. Events with no single location — a standards publication, say — and events we have not yet attributed are both counted as unattributed rather than omitted.
Sep 12, 2025
SK hynix completed HBM4 development and readied MR-MUF-based mass production on September 12, 2025, claiming over 10Gbps operating speed and 40%+ power-efficiency improvement — company-reported figures, not yet independently verified.
Apr 2025
JEDEC published JESD270-4 on 16 April 2025 specifying HBM4 at up to 8 Gb/s over a 2048-bit interface for up to 2 TB/s per stack, 32 channels per stack with two pseudo-channels each, Directed Refresh Management, 4- to 16-high stacks at 24 or 32 Gb dies for up to 64GB, and backwards compatibility with HBM3 controllers.
Sep 26, 2024
SK hynix began mass production of the world's first 12-layer HBM3E (36GB, 9.6Gbps) on September 26, 2024.
Apr 3, 2024
The facility SK hynix committed to build is located in West Lafayette, Indiana.
SK hynix signed a $3.87 billion investment agreement on April 3, 2024, for an HBM advanced-packaging facility in West Lafayette, Indiana, with Purdue University collaboration and mass production targeted for H2 2028.
Mar 19, 2024
SK hynix began volume production of the industry's first HBM3E on March 19, 2024, for supply to a customer from late March, at up to 1.18TB/s.
Feb 2024
Micron's 24GB 8-high HBM3E shipped in NVIDIA's H200 GPUs starting Q2 2024, at over 1.2TB/s bandwidth, per Micron's own product page.
Dec 6, 2023
AMD launched the Instinct MI300X accelerator with 192GB of HBM3 memory at 5.3TB/s peak bandwidth on December 6, 2023.
Mar 22, 2022
NVIDIA announced the H100 GPU with HBM3 memory ("the first GPU... to utilize HBM3, enabling 3TB/s of memory bandwidth") on March 22, 2022.
Jan 2022
JEDEC published the HBM3 DRAM standard (JESD238) in January 2022.
Oct 2013
JEDEC adopted the original HBM DRAM standard, JESD235, in October 2013, based on a 2010 proposal from AMD and SK hynix.
Date unknownno source establishes an occurrence date
Samsung reportedly passed NVIDIA's HBM3E qualification testing per one account, while a second account states formal NVIDIA approval had not yet been received — an unresolved disagreement, not a confirmed occurrence.
All 32 sources behind this page — what we read, what we tried to read and could not, and what we looked at and set aside, with the reason in view for each. A concept shared with another collection brings its own references with it, so some entries here were surfaced for a neighbouring topic rather than this one.
Original publisher links. Files open on the publisher’s site; we do not host copies. A linked document is not an additional source or an independent verification.
AMD Investor Relations · Published 2023-11-15
AMD Investor Relations · Published 2023-12-06
TSMC
Nomad Semiconductor (Substack)
Micron Technology
Wikipedia
JEDEC Solid State Technology Association · Published 2025-04-16
Phoronix · Published 2022-01-28
HotHardware
NVIDIA Newsroom · Published 2022-03-22
NVIDIA
TrendForce · Published 2025-09-22
KED Global (Korea Economic Daily) · Published 2025-09-19
SK hynix Newsroom · Published 2024-03-19
SK hynix Newsroom · Published 2024-09-26
SK hynix Newsroom · Published 2025-09-12
SK hynix Newsroom · Published 2024-04-03
PatSnap Eureka
Wevolver
We attempted these and were refused or served nothing. Nothing on this page rests on them; they are published so the gaps are checkable rather than invisible.
These came up while researching and were deliberately not used. We do not claim to have read them — each is listed with why it was passed over, so the shape of the survey is visible and not just its conclusions.
What this page does and does not claim.
Sprint 4A.1 corrected corpus: 11 events and 6 concepts. Every assertion cites at least one source this session actually fetched and read; search-result-only and blocked sources are retained only as honest references, never as sole evidence. Excludes routine marketing releases and excludes at least one researched candidate (TSMC CoWoS packaging-capacity figures) for insufficient sourcing — see the Sprint 4A.1 acceptance report. The Samsung/NVIDIA qualification event models genuine, unresolved uncertainty (reported vs. not-yet-formally-approved) rather than a false event-date conflict. Not yet publicly published; every event/concept/company row and assertion here is draft/pending-review only.
Source check, 2026-09-17. Numeric-presence checks passed for 18 assertions using available source text, which may be cached. This is not verification of their meaning. What this check does and does not prove →
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