When Memory Became a Logic Chip

An HBM stack has always had a die at the bottom that is not memory. It carries the memory controller, power delivery, refresh and the protocol conversion between the stack and the processor. Through HBM3E it was fabricated on a memory maker's own process, and nobody outside the industry had reason to think about it.

In April 2024 SK hynix and TSMC signed a memorandum of understanding to build the HBM4 base die on TSMC's advanced logic foundry process instead, stating the purpose plainly: to pack additional functionality into limited space, and to produce customised HBM for varying customer performance and power requirements. Samsung reached the same place by a different route, putting its HBM4 base die on a 4nm logic process alongside a 1c DRAM process for the memory, and saying it took that leap rather than the conventional path of proven designs in order to secure performance headroom.

That is a structural change, not an incremental one. A memory manufacturer needing a leading-edge logic die becomes a foundry customer or must run a foundry itself. The base die's process now moves with the logic roadmap rather than the DRAM roadmap. And because logic is where you put the things that differ between customers, the memory stack stops being a catalogue part.

The clearest evidence of what that bought is the gap between the standard and the parts. JEDEC published JESD270-4 on 16 April 2025 specifying HBM4 at up to 8 Gb/s across a 2048-bit interface for total bandwidth up to 2 TB/s, doubling channels per stack from 16 to 32, and — the clause that shows what a standard is for — staying backwards compatible with existing HBM3 controllers. Ten months later Samsung began mass production at 11.7 Gbps, describing that in its own announcement as roughly 46% above the 8 Gbps industry standard, reaching a maximum 3.3 TB/s per stack against a specified 2. Micron, meanwhile, is reported working to a pin speed set by revised NVIDIA specifications rather than by JEDEC.

So the published standard functions as a floor and an interoperability contract while the real target is set by the largest customer — and the logic base die is the part of the stack where a vendor can exceed the floor and a buyer can ask for something the standard never contemplated. Samsung puts HBM4E sampling in the second half of 2026 and custom HBM samples with customers in 2027, tied explicitly to hyperscaler ASIC development.

Where it goes next was set out at Hot Chips in 2026 in three phases: first the memory controller, a defect-remapping table and a custom die-to-die interface move onto the logic die; then sensors, test blocks, external memory PHYs and in-memory compute; then HBM stacked directly on the compute chip, which would abolish the distinction between memory and processor package. The independent account carrying that roadmap also carried the two objections that would stop it — thermals, by analogy with stacked-cache processors that clock lower than their flat equivalents, and doubt that processing elements on a base die can hold enough cache to be useful.

What is reported rather than announced is marked as such throughout. Process nodes for the generation after HBM4, named hyperscaler qualifications, yield percentages and the claim that a foundry has turned over half a leading-edge node's capacity to memory base dies all circulate widely; none of them is asserted here.