{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm","topic":{"slug":"custom-hbm","name":"When Memory Became a Logic Chip","description":"A sourced reference collection on the change that reframed high-bandwidth memory — the die at the bottom of the stack moving off a memory process onto a foundry logic process, which turned memory makers into foundry customers, made the stack customisable per buyer, and let vendors ship parts far faster than the standard they are built to.","coverage_notes":"Eleventh packet, and the first that extends a concept another collection already defined rather than restating it: the HBM packet describes what a base die does, and this one records that it stopped being made like memory. Ten sources were consulted: five were retrieved and read, and five were surfaced and set aside with a stated reason. Two of the reads did not come back to the automated fetcher — one returned HTTP 403, one timed out — and were opened in a browser instead; no paywall, registration wall or challenge was circumvented anywhere in this collection. The source base is unusually solid for a subject this heavily speculated about: a standards body's own announcement, two memory manufacturers' own releases, and two independent technical reports. The central finding is measurable from primaries on both sides — JEDEC specifies 8 Gb/s and up to 2 TB/s, Samsung ships 11.7 Gbps and 3.3 TB/s and itself describes that as about 46% above the standard — which is why it is asserted rather than characterised. Everything reported rather than announced is attributed as a report in the text: SK hynix's 12nm base-die node appears in trade coverage and not in its own release; a mass-production yield percentage and a system-in-package qualification for a hyperscaler's accelerator are reported, not confirmed by the parties; and process nodes for the generation after HBM4 are set aside entirely. Named gaps, in order of value: reports that a foundry has directed more than half of a leading-edge node's capacity to memory base dies, which if verified would be the most consequential second-order effect of this whole shift and is the largest hole here; Micron's own HBM4 disclosure, whose absence means the third of the three suppliers appears only through a trade report and its base-die process choice is not established at all; the JESD270-4 document itself, available on registration and not downloaded, so the standard's figures come from JEDEC's summary of it rather than its clauses; and the Hot Chips presentation behind the three-phase base-die roadmap, which reaches this page through an independent write-up whose author's scepticism is carried alongside it. Not yet editor-reviewed; every assertion reads as reported.","primer":"An HBM stack has always had a die at the bottom that is not memory. It carries the memory controller, power delivery, refresh and the protocol conversion between the stack and the processor. Through HBM3E it was fabricated on a memory maker's own process, and nobody outside the industry had reason to think about it.\n\nIn April 2024 SK hynix and TSMC signed a memorandum of understanding to build the HBM4 base die on TSMC's advanced logic foundry process instead, stating the purpose plainly: to pack additional functionality into limited space, and to produce customised HBM for varying customer performance and power requirements. Samsung reached the same place by a different route, putting its HBM4 base die on a 4nm logic process alongside a 1c DRAM process for the memory, and saying it took that leap rather than the conventional path of proven designs in order to secure performance headroom.\n\nThat is a structural change, not an incremental one. A memory manufacturer needing a leading-edge logic die becomes a foundry customer or must run a foundry itself. The base die's process now moves with the logic roadmap rather than the DRAM roadmap. And because logic is where you put the things that differ between customers, the memory stack stops being a catalogue part.\n\nThe clearest evidence of what that bought is the gap between the standard and the parts. JEDEC published JESD270-4 on 16 April 2025 specifying HBM4 at up to 8 Gb/s across a 2048-bit interface for total bandwidth up to 2 TB/s, doubling channels per stack from 16 to 32, and — the clause that shows what a standard is for — staying backwards compatible with existing HBM3 controllers. Ten months later Samsung began mass production at 11.7 Gbps, describing that in its own announcement as roughly 46% above the 8 Gbps industry standard, reaching a maximum 3.3 TB/s per stack against a specified 2. Micron, meanwhile, is reported working to a pin speed set by revised NVIDIA specifications rather than by JEDEC.\n\nSo the published standard functions as a floor and an interoperability contract while the real target is set by the largest customer — and the logic base die is the part of the stack where a vendor can exceed the floor and a buyer can ask for something the standard never contemplated. Samsung puts HBM4E sampling in the second half of 2026 and custom HBM samples with customers in 2027, tied explicitly to hyperscaler ASIC development.\n\nWhere it goes next was set out at Hot Chips in 2026 in three phases: first the memory controller, a defect-remapping table and a custom die-to-die interface move onto the logic die; then sensors, test blocks, external memory PHYs and in-memory compute; then HBM stacked directly on the compute chip, which would abolish the distinction between memory and processor package. The independent account carrying that roadmap also carried the two objections that would stop it — thermals, by analogy with stacked-cache processors that clock lower than their flat equivalents, and doubt that processing elements on a base die can hold enough cache to be useful.\n\nWhat is reported rather than announced is marked as such throughout. Process nodes for the generation after HBM4, named hyperscaler qualifications, yield percentages and the claim that a foundry has turned over half a leading-edge node's capacity to memory base dies all circulate widely; none of them is asserted here.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":5,"inspected_source_count":5,"consulted_reference_count":15,"blocked_reference_count":2,"set_aside_reference_count":13},"figures":[{"kind":"time-series","title":"The standard, and what shipped","caption":"HBM pin speed: the previous generation's maximum, the HBM4 standard's ceiling, and the part in mass production. The middle bar is the specification, not the limit.","sourceNote":"HBM3E maximum pin speed of 9.6 Gbps and shipped HBM4 at 11.7 Gbps (capable of 13) from Samsung's own February 2026 announcement; the 8 Gb/s figure from JEDEC's April 2025 announcement of JESD270-4. Samsung itself states the 11.7 figure exceeds the 8 Gbps standard by approximately 46%.","unit":"Pin speed, gigabits per second","points":[{"label":"HBM3E maximum","value":9.6,"display":"9.6 Gbps"},{"label":"HBM4 standard ceiling","value":8,"display":"8 Gb/s"},{"label":"Shipped HBM4","value":11.7,"display":"11.7 Gbps"}]},{"kind":"time-series","title":"Bandwidth per stack, specified against shipped","caption":"Total bandwidth from one HBM4 stack. The standard says up to two terabytes a second; the part in production reaches three point three.","sourceNote":"Up to 2 TB/s from JEDEC's April 2025 announcement of JESD270-4; a maximum of 3.3 TB/s per single stack, stated as 2.7x HBM3E, from Samsung's February 2026 announcement. SK hynix is separately reported at bandwidth exceeding 2 TB/s, which is not plotted because it is a floor rather than a figure.","unit":"Bandwidth per stack, terabytes per second","points":[{"label":"JESD270-4 specified maximum","value":2,"display":"2 TB/s"},{"label":"Samsung HBM4 in production","value":3.3,"display":"3.3 TB/s"}]}],"blocked_references":[{"title":"JEDEC finalizes HBM4 memory standard with major bandwidth and efficiency upgrades","publisher":"Tom's Hardware","url":"https://www.tomshardware.com/pc-components/ram/jedec-finalizes-hbm4-memory-standard-with-major-bandwidth-and-efficiency-upgrades","source_type":"journalism","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"JEDEC Releases HBM4 Standard to Advance AI and HPC Memory","publisher":"HPCwire","url":"https://www.hpcwire.com/off-the-wire/jedec-releases-hbm4-standard-to-advance-ai-and-hpc-memory/","source_type":"journalism","retrieval_status":"blocked_403","content_inspected":false,"published_at":null}],"set_aside_references":[{"title":"AWS Trainium2 chips for building LLMs are now generally available","publisher":"TechCrunch","url":"https://techcrunch.com/2024/12/03/aws-trainium2-chips-for-building-llms-are-now-generally-available-with-trainium3-coming-in-late-2025","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"AWS Trainium3 specification and re:Invent 2025 announcements","publisher":"Amazon Web Services","url":"https://aws.amazon.com/ai/machine-learning/trainium/","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Get the latest on AWS AI Chips from re:Invent 2025","publisher":"Amazon Web Services (community content)","url":"https://builder.aws.com/content/37FzTD9aYF6SIHE421joJaN2Hgv/get-the-latest-on-aws-ai-chips-from-reinvent-2025","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Google TPUv7: The 900lb Gorilla In the Room","publisher":"SemiAnalysis","url":"https://newsletter.semianalysis.com/p/tpuv7-google-takes-a-swing-at-the","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"Google Unveils 7th-Gen TPU Ironwood with 9,216-Chip Superpod","publisher":"TrendForce","url":"https://www.trendforce.com/news/2025/11/07/news-google-unveils-7th-gen-tpu-ironwood-with-9216-chip-superpod-taking-aim-at-nvidia/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"Google unveils Ironwood, seventh generation TPU, competing with Nvidia","publisher":"CNBC","url":"https://www.cnbc.com/2025/11/06/google-unveils-ironwood-seventh-generation-tpu-competing-with-nvidia.html","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"Ironwood TPUs and new Axion-based VMs for your AI workloads","publisher":"Google","url":"https://cloud.google.com/blog/products/compute/ironwood-tpus-and-new-axion-based-vms-for-your-ai-workloads","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"JESD270-4 High Bandwidth Memory (HBM4) DRAM standard","publisher":"JEDEC","url":"https://www.jedec.org/standards-documents/docs/jesd270-4","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"Meta's own MTIA roadmap disclosure","publisher":"Meta","url":"https://ai.meta.com/blog/","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Micron HBM4 product disclosure","publisher":"Micron Technology","url":"https://www.micron.com/products/memory/hbm","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Reports that Samsung Foundry has allocated over half its 4nm capacity to HBM4 base dies","publisher":"Various trade outlets","url":"https://www.techtimes.com/articles/326959/20260908/samsung-foundry-pivots-half-4nm-capacity-hbm4-external-customers-compete-own-fab.htm","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"Samsung's Hot Chips 2026 HBM base die presentation","publisher":"Hot Chips","url":"https://hotchips.org/","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"TrendForce reports on HBM4E logic-die process nodes","publisher":"TrendForce","url":"https://www.trendforce.com/news/2026/03/20/news-sk-hynix-reportedly-weighs-tsmc-3nm-for-hbm4e-logic-dies-to-gain-edge-over-samsung/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false}],"concepts":[{"slug":"cowos","name":"CoWoS (Chip-on-Wafer-on-Substrate)","category":"packaging_technology","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#cowos","assertions":[]},{"slug":"custom-ai-asic","name":"Custom AI ASIC","category":"component","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#custom-ai-asic","assertions":[]},{"slug":"custom-hbm","name":"Custom HBM","category":"memory_technology","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#custom-hbm","assertions":[{"id":"730757f0-78e0-45d6-8563-c63833f243c3","predicate":"concept.description","statement":"Because the base die is a logic die, memory stops being a catalogue part: SK hynix stated customisation as the purpose of the foundry shift, and Samsung puts HBM4E sampling in the second half of 2026 and custom HBM samples with customers in 2027, tied to hyperscaler ASIC development.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"3559b8f8-9475-4d0e-8d56-7d10510b0439","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Samsung Ships Industry-First Commercial HBM4 With Ultimate Performance for AI Computing","publisher":"Samsung Electronics","url":"https://news.samsung.com/global/samsung-ships-industry-first-commercial-hbm4-with-ultimate-performance-for-ai-computing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-02-12","documents":[]}},{"id":"6f4b9d67-82f5-4881-b933-5e6c9876ac7f","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"SK hynix Partners with TSMC to Strengthen HBM Technological Leadership","publisher":"SK hynix","url":"https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":"2024-04-19","documents":[]}}]}]},{"slug":"dram-process-node","name":"DRAM Process Node","category":"process","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#dram-process-node","assertions":[]},{"slug":"hbm-base-die","name":"HBM Base Die (Buffer Die)","category":"component","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#hbm-base-die","assertions":[{"id":"6c9c9105-8944-4af5-be07-9278013a7d0b","predicate":"concept.description","statement":"Samsung's stated base-die roadmap has three phases — memory controller, remapping table and custom die-to-die interface; then sensors, test blocks, external memory PHYs and in-memory compute; then stacking HBM directly on compute — against which the independent account raises thermals, citing AMD 3D cache parts clocking lower, and doubts near-memory compute on cache-capacity grounds.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"488f7f74-512f-4f4b-9836-8ae6e917cbdf","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Hot Chips 2026: Samsung and HBM Base Die Opportunities","publisher":"Chips and Cheese","url":"https://chipsandcheese.com/p/hot-chips-2026-samsung-and-hbm-base","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-08-23","documents":[]}},{"id":"871d985f-bf60-41f2-a0d7-8f45925b65ac","stance":"qualifies","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Hot Chips 2026: Samsung and HBM Base Die Opportunities","publisher":"Chips and Cheese","url":"https://chipsandcheese.com/p/hot-chips-2026-samsung-and-hbm-base","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-08-23","documents":[]}}]},{"id":"6e87ab43-acaf-4436-b363-a72e2196cdff","predicate":"concept.description","statement":"The HBM base die moved off a memory process onto a foundry logic process — SK hynix adopting TSMC's logic process for HBM4 under an April 2024 memorandum, Samsung using a 4nm logic die alongside 1c DRAM — which makes a memory maker a foundry customer and makes the stack customisable per buyer.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"79f53dbe-c49a-41a3-af2f-96cee8deed85","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Samsung Ships Industry-First Commercial HBM4 With Ultimate Performance for AI Computing","publisher":"Samsung Electronics","url":"https://news.samsung.com/global/samsung-ships-industry-first-commercial-hbm4-with-ultimate-performance-for-ai-computing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-02-12","documents":[]}},{"id":"9dba6441-2325-4266-b8de-703845168104","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"SK hynix Partners with TSMC to Strengthen HBM Technological Leadership","publisher":"SK hynix","url":"https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":"2024-04-19","documents":[]}},{"id":"c11a4b58-5cf8-4f5f-a238-4a2e952fbb31","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"The State of HBM4 Chronicled at CES 2026","publisher":"EE Times","url":"https://www.eetimes.com/the-state-of-hbm4-chronicled-at-ces-2026/","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-01-12","documents":[]}}]}]},{"slug":"high-bandwidth-memory","name":"High Bandwidth Memory (HBM)","category":"memory_technology","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#high-bandwidth-memory","assertions":[]},{"slug":"hbm4-standard","name":"The HBM4 Standard, and Shipping Past It","category":"memory_technology","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#hbm4-standard","assertions":[{"id":"0bb6e877-54f5-4d07-bef9-8f95a51e301a","predicate":"concept.description","statement":"JEDEC's JESD270-4, published 16 April 2025, specifies HBM4 at up to 8 Gb/s across a 2048-bit interface for up to 2 TB/s, doubles channels per stack from 16 to 32 with two pseudo-channels each, adds Directed Refresh Management for row-hammer mitigation, supports 4- to 16-high stacks at 24 or 32 Gb dies for up to 64GB, and stays backwards compatible with HBM3 controllers.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"80218b4d-c2ca-45cc-9e4c-3348f6e4c574","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"JEDEC and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard","publisher":"JEDEC Solid State Technology Association","url":"https://www.jedec.org/news/pressreleases/jedec%C2%AE-and-industry-leaders-collaborate-release-jesd270-4-hbm4-standard-advancing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2025-04-16","documents":[]}}]},{"id":"ea58d447-0fbb-4c56-8e2c-d107c4a5d054","predicate":"concept.description","statement":"Samsung ships HBM4 at 11.7 Gbps — by its own statement about 46% above the 8 Gbps standard — reaching 3.3 TB/s per stack against a specified 2 TB/s, while Micron is reported working to a pin speed set by revised NVIDIA specifications rather than by JEDEC: the standard is a floor, and the largest customer sets the target.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"54b91655-47ea-4b98-80e3-de0e8f3dd58f","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"JEDEC and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard","publisher":"JEDEC Solid State Technology Association","url":"https://www.jedec.org/news/pressreleases/jedec%C2%AE-and-industry-leaders-collaborate-release-jesd270-4-hbm4-standard-advancing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2025-04-16","documents":[]}},{"id":"7362f5aa-f632-49ba-a367-e0927f4e13ea","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"The State of HBM4 Chronicled at CES 2026","publisher":"EE Times","url":"https://www.eetimes.com/the-state-of-hbm4-chronicled-at-ces-2026/","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-01-12","documents":[]}},{"id":"f3c64a59-0cc1-414b-a1bc-68c78f2f8ed9","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Samsung Ships Industry-First Commercial HBM4 With Ultimate Performance for AI Computing","publisher":"Samsung Electronics","url":"https://news.samsung.com/global/samsung-ships-industry-first-commercial-hbm4-with-ultimate-performance-for-ai-computing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-02-12","documents":[]}}]}]},{"slug":"through-silicon-via","name":"Through-Silicon Via (TSV)","category":"interconnect","canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#through-silicon-via","assertions":[]}],"events":[{"slug":"samsung-hbm4-mass-production-2026","title":"A Part Ships Well Past Its Own Standard","category":"production_milestone","event_date":"2026-02-12","date_precision":"day","country":"South Korea","region":null,"canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#samsung-hbm4-mass-production-2026","assertions":[{"id":"dd9f9982-4682-477c-b0a0-12074d95593d","predicate":"event.description","statement":"Samsung began HBM4 mass production on 12 February 2026 at a consistent 11.7 Gbps — by its own statement about 46% above the 8 Gbps standard — with up to 3.3 TB/s per stack, 12-layer 24-36GB parts on a 4nm logic base die and 1c DRAM, and claimed 40% better power efficiency than HBM3E.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"7bfd5040-5676-4f68-91ba-f8bb51aa6385","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Samsung Ships Industry-First Commercial HBM4 With Ultimate Performance for AI Computing","publisher":"Samsung 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States","region":null,"canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#jedec-hbm4-jesd270-4-published-2025","assertions":[]},{"slug":"jedec-hbm4-jesd270-4-2025","title":"JEDEC Releases the HBM4 Standard (JESD270-4)","category":"standards_milestone","event_date":"2025-04-01","date_precision":"month","country":null,"region":null,"canonical_url":"https://www.manufacturing.ai/topics/custom-hbm#jedec-hbm4-jesd270-4-2025","assertions":[{"id":"a8bc8267-927f-426a-9721-a9ae0b0dff73","predicate":"event.description","statement":"JEDEC published JESD270-4 on 16 April 2025 specifying HBM4 at up to 8 Gb/s over a 2048-bit interface for up to 2 TB/s, 32 channels per stack with two pseudo-channels each, Directed Refresh Management, 4- to 16-high stacks at 24 or 32 Gb dies for up to 64GB, and backwards compatibility with HBM3 controllers.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"b2741d2b-b567-4a18-9a55-d54ee102b8d2","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"JEDEC and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard","publisher":"JEDEC Solid State Technology Association","url":"https://www.jedec.org/news/pressreleases/jedec%C2%AE-and-industry-leaders-collaborate-release-jesd270-4-hbm4-standard-advancing","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2025-04-16","documents":[]}}]}]},{"slug":"skhynix-tsmc-hbm4-base-die-mou-2024","title":"A Memory Maker Becomes a Foundry Customer","category":"partnership","event_date":"2024-04-19","date_precision":"day","country":"South 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