The Hyperscalers Build Their Own

The buyers became designers. Every major cloud operator now has an accelerator programme of its own, and on paper the parts are comparable to merchant GPUs. Google's seventh-generation TPU, Ironwood, is stated by its maker at 4,614 TFLOPs per chip with 192 GB of HBM at 7.37 TB/s, in pods of 256 or 9,216 chips — a full pod reaching 42.5 exaflops and drawing nearly 10 MW, liquid cooled. Amazon's Trainium3, Meta's MTIA 400 and 500 and Microsoft's Maia 200 are reported in the same class.

But the industry did not decentralise when this happened. It re-concentrated one layer down. Two companies, Broadcom and Marvell, are reported to account for roughly 95% of custom AI accelerator co-design, and a single foundry fabricates the output of all of it. A hyperscaler that designs its own chip to reduce dependence on a merchant GPU vendor acquires instead a dependence on a design partner it shares with its competitors, and on TSMC.

The scale of that is visible in filed numbers rather than projections. Broadcom reported first-quarter AI revenue of $8.4 billion, up 106% year on year, and guided to $10.7 billion for the next quarter, inside consolidated revenue of $19.3 billion.

What a design partner sells is increasingly a package rather than a circuit. Broadcom's platform is reported to combine TSMC's SoIC face-to-face 3D stacking with 2.5D CoWoS, enabling packages beyond 6,000 square millimetres of silicon carrying up to 12 HBM stacks, against roughly 2,500 conventionally. That is the same constraint the substrate and packaging collections describe, arriving from another direction: the accelerator outgrew the reticle, then the interposer, and now the package — and each escape needs somebody else's manufacturing capacity. A hyperscaler can specify a core. It cannot easily specify a package nobody else can build.

The claim that actually decides whether custom silicon is worth it is the one an outsider cannot check. Ironwood's 4,614 TFLOPs sits close to Blackwell's roughly 5,000 FP8 TFLOPS, so on peak arithmetic they look alike — but a widely repeated analyst estimate puts sustained utilisation at roughly 90% for TPUs on transformers against 70 to 80% for GPUs, which if true would make peak-FLOPS comparisons nearly meaningless. Google separately claims cost of ownership per Ironwood chip about 44% below a GB200 server on its own procurement, and roughly four times better price-performance than H100 instances on its own benchmarks. Every one of those is either a third-party estimate whose method was not read or a vendor's accounting of its own costs. None is asserted here.

Nor is the number everyone quotes. Broadcom's $73 billion AI backlog and its chief executive's stated line of sight to more than $100 billion of AI chip revenue in 2027 are the two most-cited figures in this sector, and neither appears in the quarterly results release. Both were said on the earnings call. They are recorded here as reported remarks and asserted nowhere — which is the single most important thing to understand about how this market is written about.

One more corrective. Announcing a custom accelerator is not the same as having one. Tesla's Dojo team was reported disbanded in August, after a D1 chip with 50 billion transistors. Microsoft's first Maia was reported to have been designed more for image processing than generative AI and never to have powered production AI services at scale, with its successor delayed about six months. Programmes fail, and the surviving ones are the ones anybody writes about.