{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/custom-ai-silicon","topic":{"slug":"custom-ai-silicon","name":"The Hyperscalers Build Their Own","description":"A sourced reference collection on custom AI accelerators — why every major cloud operator now designs its own chip, why two companies design most of them and one foundry builds all of it, and why the numbers everyone quotes about this market come from earnings calls and analyst estimates rather than from anything filed.","coverage_notes":"Fourteenth packet, and the one where the gap between what is filed and what is quoted is widest. Eight sources were consulted: three were retrieved and read, and five were surfaced and set aside with a stated reason. Two of the reads did not come back to the automated fetcher — one timed out, one returned only navigation furniture — and were opened in a browser instead; no paywall or challenge was circumvented. The governing decision on this page is what NOT to assert. Broadcom's $73 billion AI backlog and its chief executive's line of sight to more than $100 billion of AI chip revenue in 2027 are the two most-quoted numbers in this sector; neither appears in the quarterly results release that was read, both were said on an earnings call that was not retrieved, and both are recorded as attributed remarks and asserted nowhere. The figures asserted from Broadcom are the ones in the release. The same discipline applies to performance: peak FLOPS, HBM capacity and bandwidth are used because a manufacturer is the right authority for the dimensions of its own product, while the utilisation estimate, the total-cost-of-ownership ratio and the price-performance multiple — the three figures that would actually decide whether custom silicon is worth building — are a third-party estimate and two pieces of vendor self-accounting, and are asserted nowhere. There is a real asymmetry in this collection that a reader should know about: Broadcom appears with figures from its own release, while Marvell, Meta, Microsoft and AWS appear only through one trade survey, because none of their own disclosures was retrieved. That survey is unusually careful about marking its own second-hand claims, and this page carries those attributions rather than flattening them. Named gaps, in order of value: the Broadcom earnings call, where the headline numbers actually live; Marvell's own filings, whose absence is why no Marvell figure is asserted despite Marvell being one of the two companies this topic is about; Meta's and AWS's own accelerator disclosures; and the subscription analysis behind the utilisation estimate. Not yet editor-reviewed; every assertion reads as reported.","primer":"The buyers became designers. Every major cloud operator now has an accelerator programme of its own, and on paper the parts are comparable to merchant GPUs. Google's seventh-generation TPU, Ironwood, is stated by its maker at 4,614 TFLOPs per chip with 192 GB of HBM at 7.37 TB/s, in pods of 256 or 9,216 chips — a full pod reaching 42.5 exaflops and drawing nearly 10 MW, liquid cooled. Amazon's Trainium3, Meta's MTIA 400 and 500 and Microsoft's Maia 200 are reported in the same class.\n\nBut the industry did not decentralise when this happened. It re-concentrated one layer down. Two companies, Broadcom and Marvell, are reported to account for roughly 95% of custom AI accelerator co-design, and a single foundry fabricates the output of all of it. A hyperscaler that designs its own chip to reduce dependence on a merchant GPU vendor acquires instead a dependence on a design partner it shares with its competitors, and on TSMC.\n\nThe scale of that is visible in filed numbers rather than projections. Broadcom reported first-quarter AI revenue of $8.4 billion, up 106% year on year, and guided to $10.7 billion for the next quarter, inside consolidated revenue of $19.3 billion.\n\nWhat a design partner sells is increasingly a package rather than a circuit. Broadcom's platform is reported to combine TSMC's SoIC face-to-face 3D stacking with 2.5D CoWoS, enabling packages beyond 6,000 square millimetres of silicon carrying up to 12 HBM stacks, against roughly 2,500 conventionally. That is the same constraint the substrate and packaging collections describe, arriving from another direction: the accelerator outgrew the reticle, then the interposer, and now the package — and each escape needs somebody else's manufacturing capacity. A hyperscaler can specify a core. It cannot easily specify a package nobody else can build.\n\nThe claim that actually decides whether custom silicon is worth it is the one an outsider cannot check. Ironwood's 4,614 TFLOPs sits close to Blackwell's roughly 5,000 FP8 TFLOPS, so on peak arithmetic they look alike — but a widely repeated analyst estimate puts sustained utilisation at roughly 90% for TPUs on transformers against 70 to 80% for GPUs, which if true would make peak-FLOPS comparisons nearly meaningless. Google separately claims cost of ownership per Ironwood chip about 44% below a GB200 server on its own procurement, and roughly four times better price-performance than H100 instances on its own benchmarks. Every one of those is either a third-party estimate whose method was not read or a vendor's accounting of its own costs. None is asserted here.\n\nNor is the number everyone quotes. Broadcom's $73 billion AI backlog and its chief executive's stated line of sight to more than $100 billion of AI chip revenue in 2027 are the two most-cited figures in this sector, and neither appears in the quarterly results release. Both were said on the earnings call. They are recorded here as reported remarks and asserted nowhere — which is the single most important thing to understand about how this market is written about.\n\nOne more corrective. Announcing a custom accelerator is not the same as having one. Tesla's Dojo team was reported disbanded in August, after a D1 chip with 50 billion transistors. Microsoft's first Maia was reported to have been designed more for image processing than generative AI and never to have powered production AI services at scale, with its successor delayed about six months. Programmes fail, and the surviving ones are the ones anybody writes about.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":3,"inspected_source_count":3,"consulted_reference_count":30,"blocked_reference_count":4,"set_aside_reference_count":26},"figures":[{"kind":"time-series","title":"One design partner's AI revenue, as filed","caption":"Broadcom's quarterly AI semiconductor revenue, from its own results release. The second bar is guidance, not a result.","sourceNote":"Broadcom's first-quarter fiscal 2026 release of 4 March 2026, for the quarter ended 1 February 2026: Q1 AI revenue of $8.4 billion, stated as 106% growth year over year, and Q2 AI semiconductor revenue expected to be $10.7 billion. The second bar is guidance, not a result. No prior-year bar is plotted: the release states a growth RATE but does not disclose the prior-year AI figure, and back-computing it from the percentage would put a number on this page that no source states.","unit":"AI semiconductor revenue, billions of US dollars","points":[{"label":"Q1 FY2026 (actual)","value":8.4,"display":"$8.4bn"},{"label":"Q2 FY2026 (guidance)","value":10.7,"display":"$10.7bn"}]},{"kind":"time-series","title":"How much silicon fits in one package","caption":"Silicon area a package can carry, conventional 2.5D against the stacked platform used for custom accelerators. This is what the design partner is really selling.","sourceNote":"Reported May 2026: roughly 2,500 mm-squared as the limit of conventional 2.5D designs, against packages exceeding 6,000 mm-squared with up to 12 HBM stacks on Broadcom's 3.5D XDSiP platform combining TSMC SoIC with CoWoS. Both figures come from a trade survey rather than from the manufacturer.","unit":"Silicon area in one package, square millimetres","points":[{"label":"Conventional 2.5D","value":2500,"display":"~2,500 mm²"},{"label":"3.5D stacked platform","value":6000,"display":">6,000 mm²"}]}],"blocked_references":[{"title":"All AI Data Center Interconnects Will Be Optical Within 5 Years","publisher":"Semiconductor Engineering","url":"https://semiengineering.com/all-ai-data-center-interconnects-will-be-optical-within-5-years/","source_type":"journalism","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"Intel Foundry — Advanced Packaging (EMIB, Foveros)","publisher":"Intel","url":"https://www.intel.com/content/www/us/en/foundry/advanced-packaging.html","source_type":"company_website","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"NVIDIA Corporation, Annual Report on Form 10-K, fiscal year 2025 (investor-relations PDF)","publisher":"NVIDIA","url":"https://s201.q4cdn.com/141608511/files/doc_financials/2025/q4/177440d5-3b32-4185-8cc8-95500a9dc783.pdf","source_type":"regulatory_filing","retrieval_status":"retrieved_no_content","content_inspected":false,"published_at":null},{"title":"TSMC Quarterly Results, second quarter 2026 (investor relations)","publisher":"TSMC","url":"https://investor.tsmc.com/english/quarterly-results/2026/q2","source_type":"company_website","retrieval_status":"retrieved_no_content","content_inspected":false,"published_at":null}],"set_aside_references":[{"title":"AI Accelerator Chips Market Size & Share, Industry Report","publisher":"Global Market Insights","url":"https://www.gminsights.com/industry-analysis/ai-accelerator-chips-market","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"AMD touts Instinct MI430X, MI440X, and MI455X AI accelerators and Helios rack-scale AI architecture at CES","publisher":"Tom’s Hardware","url":"https://www.tomshardware.com/tech-industry/artificial-intelligence/amd-touts-instinct-mi430x-mi440x-and-mi455x-ai-accelerators-and-helios-rack-scale-ai-architecture-at-ces-full-mi400-series-family-fulfills-a-broad-range-of-infrastructure-and-customer-requirements","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"AMD unveils full MI400 product lineup, claims MI500 chips will deliver 1,000x increase","publisher":"DataCenterDynamics","url":"https://www.datacenterdynamics.com/en/news/amd-unveils-full-mi400-product-lineup-claims-mi500-chips-will-deliver-1000x-increase-in-ai-performance/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"ASIC Set to Outpace GPU? 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