CPUs and the End of Free Speed: Why Processors Stopped Getting Faster

For about thirty years processors got faster for free, and then they stopped. Understanding why requires separating two rules that are constantly confused. Moore's law is an observation about counting: Gordon Moore noted in 1965 that the number of components per integrated circuit had been doubling every year, and revised it in 1975 to roughly every two years. It says nothing about speed. Dennard scaling, from a 1974 paper co-authored by Robert H. Dennard, is the one that promised speed: as transistors shrink, their power density stays constant, so power use stays in proportion to area. Smaller meant faster and cooler at the same time.

Dennard scaling broke around 2005. Leakage current and threshold voltage do not scale with size, so power density rises as features shrink, and the industry hit what it named the power wall. Intel cancelled the Tejas and Jayhawk processors in 2004. Clock frequency has stagnated between 4 and 6 GHz ever since, with per-CPU power settling near 100 watts. Moore's law kept going; the free speed did not. Everything since is an answer to that one failure.

The first answer was more cores. Three walls forced it — the memory wall, the widening gap between processor and memory speed; the ILP wall, the difficulty of finding enough independent work inside one instruction stream; and the power wall. Dual-core parts became commonplace in personal computers in the late 2000s. But Amdahl's law caps what that buys: the gain is bounded by the fraction of the program that can actually run in parallel, and most programs are stubbornly sequential.

Which is the precise reason the accelerator exists. Matrix multiplication, the inner loop of every neural network, is close to embarrassingly parallel — one of the rare workloads for which adding arithmetic units really does add performance. A GPU is a processor that spends its transistor budget on those units instead of on the caches and control logic a CPU needs to make sequential code fast. The whole AI hardware industry sits in the gap Amdahl's law left open.

So the processor's role changed. NVIDIA's Grace CPU Superchip carries 144 Arm Neoverse V2 cores and LPDDR5X memory at up to 1 TB/s, joined to the accelerator by a 900 GB/s NVLink-C2C link — an Arm design in a data centre x86 owned for two decades, and one whose headline specification is the bandwidth of its link rather than its compute. By the Vera Rubin announcement of March 2026 the CPU is simply one of seven coordinated chips, and the rack pairs 72 accelerators with 36 processors. The CPU is no longer the machine. It is a part of one.

Whether Moore's law itself still holds is disputed, and this page leaves it disputed. Intel's chief executive said in 2015 that the cadence had slowed toward two and a half years. In September 2022 NVIDIA's chief executive declared the law dead and Intel's said the opposite days later — two interested parties whose companies' strategies depend on opposite answers.

Most readers know processors through a laptop, and the parts that run data centres differ in kind. A mainstream Ryzen 9000 desktop chip tops out at 16 cores on two memory channels. AMD's Turin server generation reaches 128 cores — or 192 of the denser variety — on twelve channels, and Venice is stated at up to 256 on sixteen, with 128 PCIe lanes so one socket can host several accelerators, a fleet of NVMe drives and a fast network card at once. Intel names the same list for what separates Xeon from Core: ECC memory, more cores, more PCIe lanes, more RAM, larger caches, and reliability features.

ECC is the difference most buyers never see and the one that matters most. Server memory carries extra check bits — 72 bits per word for 64 of data, nine chips on a DIMM side instead of eight — so a single-bit flip is corrected and a double-bit flip is at least noticed. Whether that is worth paying for depends on how often memory goes wrong, and a 2009 Google study measured between 25,000 and 70,000 errors per billion device-hours per megabit: roughly one error per gigabyte every 1.8 hours. Desktop platforms historically went without.

Server processors also reached core counts no single die could hold, and solved it the way accelerators later would. AMD's Rome generation in 2019 rebuilt the processor as eight small 7nm compute chiplets around one cheap 14nm input/output die — leading-edge silicon only where it earns its cost. The difference in motive is worth noting: AMD split the die to make a large processor economic; NVIDIA split Blackwell because the reticle limit left it no choice.

This is a starter collection and shorter than the memory and GPU pages it connects to. What is missing is named rather than implied: Dennard's 1974 paper is behind a subscription wall and is cited here only through a tertiary account, Moore's own 1965 paper was not retrieved, Arm's Neoverse page returned an error shell so the licensor's side of the Grace design is unsourced, and the cache article read here gives no cycle-latency figures, so none are quoted. AMD's and Intel's own product pages remain largely marketing; the generation tables used here come from tertiary accounts rather than from the manufacturers.