{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/cpu","topic":{"slug":"cpu","name":"CPUs and the End of Free Speed: Why Processors Stopped Getting Faster","description":"A sourced starter collection on the central processor — the two scaling laws that governed it, why one of them broke in 2005 and clock speeds stalled, what multiple cores bought and what Amdahl's law capped, and how the CPU became a component of somebody else's rack.","coverage_notes":"Fifth packet. Seeded so that the memory and GPU collections have somewhere to point when they reach for the processor, and expanded in a second pass to treat the server-versus-consumer split as a first-class subject rather than a footnote. Sixteen sources were consulted: eleven were retrieved and read, one was attempted and returned an error shell, and four were surfaced and set aside with a stated reason. The spine of the topic — Dennard scaling, Moore's law, the multicore transition, ECC, the cache hierarchy and the EPYC and Xeon generation tables — rests largely on tertiary encyclopedia accounts rather than primary papers or manufacturer documentation, which is the honest weakness of this collection and the first thing a later pass should fix: Dennard's 1974 IEEE paper is paywalled and was not circumvented, and Moore's 1965 paper was surfaced but not retrieved. AMD's own EPYC page was read in a browser and turned out to be almost entirely comparative marketing — its claims against Intel Xeon and AWS Graviton are AMD's own, made on tests AMD chose, and none is asserted here. Arm's Neoverse page returned a navigation shell, so the licensor's side of the Grace CPU is unsourced. The cache source gives no per-level cycle latencies, so none are quoted. One disagreement is published rather than resolved: NVIDIA's and Intel's chief executives took opposite public positions on whether Moore's law is dead within days of each other in September 2022, and both lead companies whose strategy depends on the answer. Not yet editor-reviewed; every assertion reads as reported.","primer":"For about thirty years processors got faster for free, and then they stopped. Understanding why requires separating two rules that are constantly confused. Moore's law is an observation about counting: Gordon Moore noted in 1965 that the number of components per integrated circuit had been doubling every year, and revised it in 1975 to roughly every two years. It says nothing about speed. Dennard scaling, from a 1974 paper co-authored by Robert H. Dennard, is the one that promised speed: as transistors shrink, their power density stays constant, so power use stays in proportion to area. Smaller meant faster and cooler at the same time.\n\nDennard scaling broke around 2005. Leakage current and threshold voltage do not scale with size, so power density rises as features shrink, and the industry hit what it named the power wall. Intel cancelled the Tejas and Jayhawk processors in 2004. Clock frequency has stagnated between 4 and 6 GHz ever since, with per-CPU power settling near 100 watts. Moore's law kept going; the free speed did not. Everything since is an answer to that one failure.\n\nThe first answer was more cores. Three walls forced it — the memory wall, the widening gap between processor and memory speed; the ILP wall, the difficulty of finding enough independent work inside one instruction stream; and the power wall. Dual-core parts became commonplace in personal computers in the late 2000s. But Amdahl's law caps what that buys: the gain is bounded by the fraction of the program that can actually run in parallel, and most programs are stubbornly sequential.\n\nWhich is the precise reason the accelerator exists. Matrix multiplication, the inner loop of every neural network, is close to embarrassingly parallel — one of the rare workloads for which adding arithmetic units really does add performance. A GPU is a processor that spends its transistor budget on those units instead of on the caches and control logic a CPU needs to make sequential code fast. The whole AI hardware industry sits in the gap Amdahl's law left open.\n\nSo the processor's role changed. NVIDIA's Grace CPU Superchip carries 144 Arm Neoverse V2 cores and LPDDR5X memory at up to 1 TB/s, joined to the accelerator by a 900 GB/s NVLink-C2C link — an Arm design in a data centre x86 owned for two decades, and one whose headline specification is the bandwidth of its link rather than its compute. By the Vera Rubin announcement of March 2026 the CPU is simply one of seven coordinated chips, and the rack pairs 72 accelerators with 36 processors. The CPU is no longer the machine. It is a part of one.\n\nWhether Moore's law itself still holds is disputed, and this page leaves it disputed. Intel's chief executive said in 2015 that the cadence had slowed toward two and a half years. In September 2022 NVIDIA's chief executive declared the law dead and Intel's said the opposite days later — two interested parties whose companies' strategies depend on opposite answers.\n\nMost readers know processors through a laptop, and the parts that run data centres differ in kind. A mainstream Ryzen 9000 desktop chip tops out at 16 cores on two memory channels. AMD's Turin server generation reaches 128 cores — or 192 of the denser variety — on twelve channels, and Venice is stated at up to 256 on sixteen, with 128 PCIe lanes so one socket can host several accelerators, a fleet of NVMe drives and a fast network card at once. Intel names the same list for what separates Xeon from Core: ECC memory, more cores, more PCIe lanes, more RAM, larger caches, and reliability features.\n\nECC is the difference most buyers never see and the one that matters most. Server memory carries extra check bits — 72 bits per word for 64 of data, nine chips on a DIMM side instead of eight — so a single-bit flip is corrected and a double-bit flip is at least noticed. Whether that is worth paying for depends on how often memory goes wrong, and a 2009 Google study measured between 25,000 and 70,000 errors per billion device-hours per megabit: roughly one error per gigabyte every 1.8 hours. Desktop platforms historically went without.\n\nServer processors also reached core counts no single die could hold, and solved it the way accelerators later would. AMD's Rome generation in 2019 rebuilt the processor as eight small 7nm compute chiplets around one cheap 14nm input/output die — leading-edge silicon only where it earns its cost. The difference in motive is worth noting: AMD split the die to make a large processor economic; NVIDIA split Blackwell because the reticle limit left it no choice.\n\nThis is a starter collection and shorter than the memory and GPU pages it connects to. What is missing is named rather than implied: Dennard's 1974 paper is behind a subscription wall and is cited here only through a tertiary account, Moore's own 1965 paper was not retrieved, Arm's Neoverse page returned an error shell so the licensor's side of the Grace design is unsourced, and the cache article read here gives no cycle-latency figures, so none are quoted. AMD's and Intel's own product pages remain largely marketing; the generation tables used here come from tertiary accounts rather than from the manufacturers.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":11,"inspected_source_count":11,"consulted_reference_count":14,"blocked_reference_count":1,"set_aside_reference_count":13},"figures":[{"kind":"time-series","title":"Cores per socket, when the clock stopped rising","caption":"Maximum cores in one AMD EPYC socket by generation. Frequency has been flat since 2005; this is where the performance went instead.","sourceNote":"Wikipedia's Epyc article, read directly — a tertiary account of specifications AMD publishes only as scattered marketing. The 2026 Venice figure is a stated specification for a generation at the start of its life, not a shipped measurement.","unit":"Maximum cores per socket","points":[{"label":"Naples 2017","value":32,"display":"32"},{"label":"Rome 2019","value":64,"display":"64"},{"label":"Milan 2021","value":64,"display":"64"},{"label":"Genoa 2022","value":96,"display":"96"},{"label":"Turin 2024","value":192,"display":"192"},{"label":"Venice 2026","value":256,"display":"256"}]},{"kind":"time-series","title":"Where server and consumer parts diverge","caption":"Memory channels per socket. This is the difference that is hardest to see on a spec comparison and hardest to work around: many cores are useless if you cannot feed them.","sourceNote":"Wikipedia's Ryzen and Epyc articles, both read directly. Consumer and Threadripper figures from the Ryzen article; server figures from the Epyc article. Stated platform specifications, not measurements.","unit":"Memory channels per socket","points":[{"label":"Ryzen desktop","value":2,"display":"2"},{"label":"Threadripper","value":4,"display":"4"},{"label":"EPYC Genoa/Turin","value":12,"display":"12"},{"label":"EPYC Venice","value":16,"display":"16"}]},{"kind":"time-series","title":"Two laws, one of which stopped","caption":"Clock frequency stopped rising when Dennard scaling failed. The band since 2005 is a ceiling, not a trend — the figure shows the stated stagnation range rather than any single part.","sourceNote":"Wikipedia's Dennard scaling article, read directly. It states clock frequency has stagnated at 4–6 GHz and CPU power at around 100 W TDP since 2005; the two columns show the low and high ends of that stated range, not measured products.","unit":"Clock frequency, GHz (stated stagnation band since 2005)","points":[{"label":"Band, low","value":4,"display":"4 GHz"},{"label":"Band, high","value":6,"display":"6 GHz"}]}],"blocked_references":[{"title":"Arm Neoverse (computing infrastructure)","publisher":"Arm","url":"https://www.arm.com/markets/computing-infrastructure/neoverse","source_type":"company_website","retrieval_status":"retrieved_no_content","content_inspected":false,"published_at":null}],"set_aside_references":[{"title":"1970 1-Kbit DRAM (Intel, U.S.A.)","publisher":"Semiconductor History Museum of Japan","url":"https://www.shmj.or.jp/english/pdf/ic/exhibi738E.pdf","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"Arm Neoverse V3 processor documentation","publisher":"Arm","url":"https://developer.arm.com/Processors/Neoverse%20V3","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Back to the Future: The 1103 Commercial DRAM has Landed","publisher":"Rochester Electronics","url":"https://www.rocelec.com/news/back-to-the-future-the-1103-commercial","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Cramming more components onto integrated circuits (Moore, 1965)","publisher":"Electronics Magazine, via Intel","url":"https://newsroom.intel.com/wp-content/uploads/sites/11/2018/05/moores-law-electronics.pdf","source_type":"academic","retrieval_status":"search_result_only","content_inspected":false},{"title":"Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions (Dennard et al., 1974)","publisher":"IEEE Journal of Solid-State Circuits","url":"https://ieeexplore.ieee.org/document/1050511","source_type":"academic","retrieval_status":"search_result_only","content_inspected":false},{"title":"Dynamic Random Access Memory (DRAM) Explained — All About Semiconductor","publisher":"Samsung Semiconductor (YouTube)","url":"https://www.youtube.com/watch?v=_pdwsakYhMk","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Intel Xeon Processors","publisher":"Intel","url":"https://www.intel.com/content/www/us/en/products/details/processors/xeon.html","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Memory lane","publisher":"Nature Electronics","url":"https://www.nature.com/articles/s41928-018-0098-9","source_type":"academic","retrieval_status":"search_result_only","content_inspected":false},{"title":"NVIDIA Blackwell Architecture Explained: B200, GB200 & PCB Design Impact","publisher":"NextPCB","url":"https://www.nextpcb.com/blog/nvidia-blackwell-architecture-b200-gb200-pcb-design","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"NVIDIA GPU History: GeForce 256 to Vera Rubin","publisher":"IOH Tech","url":"https://iohtechco.com/resources/nvidia-gpu-history-evolution","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"Robert H. Dennard of IBM Invents DRAM","publisher":"HistoryOfInformation.com","url":"https://www.historyofinformation.com/detail.php?id=840","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"Robert H. Dennard, National Inventors Hall of Fame Inductee","publisher":"National Inventors Hall of Fame","url":"https://www.invent.org/inductees/robert-h-dennard","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"What is CUDA? Parallel programming for GPUs","publisher":"InfoWorld","url":"https://www.infoworld.com/article/2256401/what-is-cuda-parallel-programming-for-gpus.html","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false}],"concepts":[{"slug":"chiplet","name":"Chiplet","category":"component","canonical_url":"https://www.manufacturing.ai/topics/cpu#chiplet","assertions":[]},{"slug":"dennard-scaling","name":"Dennard Scaling","category":"process","canonical_url":"https://www.manufacturing.ai/topics/cpu#dennard-scaling","assertions":[{"id":"cc84581c-41cb-43a5-8ab1-83360f904db1","predicate":"concept.description","statement":"Dennard scaling, from a 1974 paper co-authored by Robert H. Dennard, held that shrinking transistors keeps power density constant; it broke down around 2005 because leakage current and threshold voltage do not scale, stalling clock frequency at 4–6 GHz and per-CPU power near 100 W.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"41a8aa8a-6bf8-45cf-b033-64319dfda485","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Dennard scaling","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Dennard_scaling","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]}]},{"slug":"dram-cell","name":"DRAM Cell (1T1C)","category":"component","canonical_url":"https://www.manufacturing.ai/topics/cpu#dram-cell","assertions":[]},{"slug":"ecc-memory","name":"ECC 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failed.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"39cad5a8-ed1a-40db-bbdf-dbd795914124","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Moore's law","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Moore%27s_law","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]},{"id":"4e1188a6-515c-47d8-aaf4-5a4aac7fbf9d","predicate":"concept.description","statement":"Moore's law's continuation is disputed by interested parties: Intel's chief executive said in 2015 the cadence had slowed toward two and a half years, and in September 2022 NVIDIA's chief executive declared the law dead while Intel's contradicted him within days.","assessment":"disputed","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"cf8142dc-8e5b-483c-bea9-d68729365c3e","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Moore's law","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Moore%27s_law","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"f8950c71-3924-4b91-ab12-512d4f90db0b","stance":"challenges","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Moore's law","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Moore%27s_law","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]}]},{"slug":"multicore-and-amdahls-ceiling","name":"Multicore and Amdahl's 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(2026).","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"03f7b36a-e900-4945-a73f-acfbd21e886a","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"AMD EPYC Server CPUs","publisher":"AMD","url":"https://www.amd.com/en/products/processors/server/epyc.html","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"bc6237d3-26c5-4bbc-bd7b-33acfdff6340","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Epyc","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Epyc","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]}]},{"slug":"server-versus-consumer-cpu","name":"Server Versus Consumer Processors","category":"component","canonical_url":"https://www.manufacturing.ai/topics/cpu#server-versus-consumer-cpu","assertions":[{"id":"292aad72-e78c-445d-986a-3b1d4feabc1b","predicate":"concept.description","statement":"A mainstream consumer Ryzen desktop part reaches 16 cores on two memory channels; AMD's server generations reach 128–192 cores on twelve channels and up to 256 on sixteen, with 128 PCIe lanes — and Intel names ECC, core count, PCIe lanes, RAM capacity, cache size and RAS as what separates Xeon from Core.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"8884e0e5-618e-44cb-a6ba-05072e1fd57f","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Ryzen","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Ryzen","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"ab378cc8-29dc-49bc-b70b-dc81e6d0d9d8","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Xeon","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Xeon","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"fbe358f7-18e5-4826-bf1f-7b87da4779b9","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Epyc","publisher":"Wikipedia","url":"https://en.wikipedia.org/wiki/Epyc","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]}]},{"slug":"cpu-cache-hierarchy","name":"The Cache Hierarchy","category":"component","canonical_url":"https://www.manufacturing.ai/topics/cpu#cpu-cache-hierarchy","assertions":[{"id":"50c9bf68-0e81-4f8f-b0ba-6e8c87fb016e","predicate":"concept.description","statement":"The L1/L2/L3 cache hierarchy exists to hide the memory wall — a modern CPU can execute hundreds of instructions in the time taken to fetch one cache line from main memory — and spending transistors on caches rather than arithmetic units is the exact inverse of the GPU's bargain.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"38f3b41d-c01a-4bdc-b4de-e11ff0d5610f","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"CPU 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Vera Rubin Opens Agentic AI Frontier","publisher":"NVIDIA","url":"https://nvidianews.nvidia.com/news/nvidia-vera-rubin-platform","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-03-16","documents":[]}}]},{"id":"7b349c96-95b1-4f33-9dfb-aa4da41895f3","predicate":"concept.description","statement":"NVIDIA's Grace CPU Superchip pairs 144 Arm Neoverse V2 cores and LPDDR5X memory at up to 1 TB/s with a 900 GB/s NVLink-C2C link to the accelerator — an Arm design in an x86 data centre, specified around the bandwidth of that link rather than around compute.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"dfa7d724-44db-4c3e-867a-e187c5ccb932","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"NVIDIA Grace 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