The copper collection in this index establishes that a high-speed electrical signal degrades over a few feet. This page is the same physics one level down, on the circuit board, where the numbers are smaller and stranger.
A high-speed link has a fixed allowance of signal it can afford to lose, and that allowance shrank exactly as the data rate doubled. Two vendors who compete with each other state the same standards-derived budgets: 36 dB for PCIe 5.0 and 32 dB for PCIe 6.0, at a 16 GHz Nyquist frequency. The reason is the encoding. PCIe 6.0 moved to PAM4, carrying two bits per clock cycle across four amplitude levels rather than one bit across two — which is what makes 64 GT/s possible, and which costs roughly 9 dB of signal-to-noise and about a third of the timing interval, because you cannot double the voltage levels and the voltage budget at the same time. Forward error correction and fixed-size packets were added to cope.
The specification's physical targets did not relax to compensate: roughly 12 to 14 inches of trace on the motherboard plus 3 to 4 on an add-in card, about 18 inches in total, essentially unchanged from PCIe 5.0. A harder signalling problem, the same distance, less margin.
So the reach collapses. On PCIe 6.0, board reach without a retimer is stated at 4.3 inches on low-loss circuit-board material and 7.1 inches on ultra-low-loss — against a specification that assumes about eighteen. With a retimer, roughly double: 9.9 and 15.1 inches. That gap is the entire commercial case for a category of chip whose only job is to buy back distance the physics took away.
The mechanism explains why a cheaper part will not do. A redriver amplifies what it receives, noise included. A retimer uses clock data recovery to reconstruct the data stream and retransmit a fresh copy on a clean clock, which resets the jitter and insertion-loss budgets and lets the channel run to twice the original specification. A redriver cannot reset random jitter and adds thermal noise of its own. The retimer costs more power and more latency, which is why both parts still exist — and why one supplier now builds them to a shared mechanical footprint so an architect can swap one for the other without redesigning the board. That is a tacit admission that nobody knows at design time how much reach a topology will need.
What this is worth commercially shows up in margin. Astera Labs reported $392.4 million of revenue for the quarter ended 30 June 2026, up 104% year on year, at a 73.3% GAAP gross margin, guiding to $540–560 million. A gross margin above 73% on signal-conditioning silicon is what a hard-to-substitute component earns when the thing it enables is scarce. The category has widened with the rack: from retimers to fabric switches with hundreds of lanes, CXL memory controllers, Ethernet conditioners at 1.6 and 3.2 terabits, cable modules carrying PCIe seven metres where passive cable manages about three, and announced optical work.
One caution belongs in the text rather than a footnote. Every technical account read for this page was written by a company that sells the part it describes — including the one on a trade publication's site, which is labelled a sponsor blog and written by a product marketing director at an IP vendor. Two competitors stating the same loss budgets is real corroboration, and those budgets are set by a standards body rather than by either of them. But the inference everyone draws from them — that a system needs a retimer — comes only from people selling retimers, and the specification itself was not read.