{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon","topic":{"slug":"connectivity-silicon","name":"Signals That Do Not Reach","description":"A sourced reference collection on the small chips that exist because copper traces are too short — why the usable reach of a PCIe 6.0 trace is measured in inches, what a retimer actually does to a signal, and why the least glamorous silicon in an AI rack earns a gross margin above 70%.","coverage_notes":"Sixteenth packet, and the one with the weakest independence in the index — which is stated here rather than left to be discovered. Nine sources were consulted: four were retrieved and read, and five were surfaced and set aside with a stated reason. Two of the reads did not come back to the automated fetcher — one timed out, one returned HTTP 403 — and were opened in a browser instead; no paywall or challenge was circumvented. EVERY technical account read for this collection was written by a company that sells the component it describes. That includes the source carried on a trade publication's domain, which is explicitly labelled a sponsor blog and written by a product marketing director at an IP vendor; this page names that provenance in its own text and not only in the register. There is genuine corroboration in one respect: two competing vendors independently state the same loss budgets, 36 dB for PCIe 5.0 and 32 dB for PCIe 6.0 at a 16 GHz Nyquist frequency, and those budgets are set by a standards body rather than by either company. But corroboration between two interested parties on a third party's numbers is not verification, and the conclusion both draw — that a system needs a retimer — has no independent support here at all. The counter-arguments a neutral source would supply, such as how often designers instead use better board material, shorten the topology or accept a redriver's limitations, are absent. The commercial figures come from one company's own results release, which describes itself as preliminary. Named gaps, in order of value: the PCI-SIG specification, which would replace four interested accounts of the loss budget with the document that sets it; the supplier's filed report, which would carry the customer-concentration disclosure that is the critical risk for a company this dependent on a few hyperscalers and is the single most important thing not established here; a third supplier's product line, whose absence means this page describes a competitive market through one company's results; the UALink specification, which is why this page can say what one supplier built for UALink without saying what UALink is; and the incumbent merchant PCIe switch vendors, whose absence is why no market-share figure appears anywhere on this page. Not yet editor-reviewed; every assertion reads as reported.","primer":"The copper collection in this index establishes that a high-speed electrical signal degrades over a few feet. This page is the same physics one level down, on the circuit board, where the numbers are smaller and stranger.\n\nA high-speed link has a fixed allowance of signal it can afford to lose, and that allowance shrank exactly as the data rate doubled. Two vendors who compete with each other state the same standards-derived budgets: 36 dB for PCIe 5.0 and 32 dB for PCIe 6.0, at a 16 GHz Nyquist frequency. The reason is the encoding. PCIe 6.0 moved to PAM4, carrying two bits per clock cycle across four amplitude levels rather than one bit across two — which is what makes 64 GT/s possible, and which costs roughly 9 dB of signal-to-noise and about a third of the timing interval, because you cannot double the voltage levels and the voltage budget at the same time. Forward error correction and fixed-size packets were added to cope.\n\nThe specification's physical targets did not relax to compensate: roughly 12 to 14 inches of trace on the motherboard plus 3 to 4 on an add-in card, about 18 inches in total, essentially unchanged from PCIe 5.0. A harder signalling problem, the same distance, less margin.\n\nSo the reach collapses. On PCIe 6.0, board reach without a retimer is stated at 4.3 inches on low-loss circuit-board material and 7.1 inches on ultra-low-loss — against a specification that assumes about eighteen. With a retimer, roughly double: 9.9 and 15.1 inches. That gap is the entire commercial case for a category of chip whose only job is to buy back distance the physics took away.\n\nThe mechanism explains why a cheaper part will not do. A redriver amplifies what it receives, noise included. A retimer uses clock data recovery to reconstruct the data stream and retransmit a fresh copy on a clean clock, which resets the jitter and insertion-loss budgets and lets the channel run to twice the original specification. A redriver cannot reset random jitter and adds thermal noise of its own. The retimer costs more power and more latency, which is why both parts still exist — and why one supplier now builds them to a shared mechanical footprint so an architect can swap one for the other without redesigning the board. That is a tacit admission that nobody knows at design time how much reach a topology will need.\n\nWhat this is worth commercially shows up in margin. Astera Labs reported $392.4 million of revenue for the quarter ended 30 June 2026, up 104% year on year, at a 73.3% GAAP gross margin, guiding to $540–560 million. A gross margin above 73% on signal-conditioning silicon is what a hard-to-substitute component earns when the thing it enables is scarce. The category has widened with the rack: from retimers to fabric switches with hundreds of lanes, CXL memory controllers, Ethernet conditioners at 1.6 and 3.2 terabits, cable modules carrying PCIe seven metres where passive cable manages about three, and announced optical work.\n\nOne caution belongs in the text rather than a footnote. Every technical account read for this page was written by a company that sells the part it describes — including the one on a trade publication's site, which is labelled a sponsor blog and written by a product marketing director at an IP vendor. Two competitors stating the same loss budgets is real corroboration, and those budgets are set by a standards body rather than by either of them. But the inference everyone draws from them — that a system needs a retimer — comes only from people selling retimers, and the specification itself was not read.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":4,"inspected_source_count":4,"consulted_reference_count":7,"blocked_reference_count":0,"set_aside_reference_count":7},"figures":[{"kind":"share-comparison","title":"What a retimer buys, in inches","caption":"PCIe 6.0 system board reach with and without a retimer, on two grades of circuit-board material. The specification assumes roughly eighteen inches of total trace.","sourceNote":"Figures stated by Astera Labs, a retimer vendor: without a retimer, 4.3 inches on low-loss PCB material and 7.1 inches on ultra-low-loss; with a retimer, 9.9 and 15.1 inches respectively. No independent source for these specific reach numbers was retrieved, and the underlying PCI-SIG specification was not read.","points":["Low-loss PCB","Ultra-low-loss PCB"],"seriesA":{"label":"Without a retimer","values":[4.3,7.1]},"seriesB":{"label":"With a retimer","values":[9.9,15.1]},"gapLabel":"The distance the component buys back"},{"kind":"time-series","title":"One connectivity supplier's quarterly revenue","caption":"Astera Labs revenue by quarter, from its own results release. The third bar is guidance, not a result.","sourceNote":"From the company's second-quarter 2026 release of 4 August 2026, which describes its figures as preliminary: revenue of $392.4 million for the quarter ended 30 June 2026, stated as up 27% sequentially — the prior quarter is therefore plotted from the separately reported $308.4 million — and third-quarter guidance of $540 million to $560 million, plotted at the lower bound of that range.","unit":"Quarterly revenue, millions of US dollars","points":[{"label":"Q1 2026","value":308.4,"display":"$308.4m"},{"label":"Q2 2026","value":392.4,"display":"$392.4m"},{"label":"Q3 2026 (guidance)","value":540,"display":"$540–560m"}]}],"blocked_references":[],"set_aside_references":[{"title":"Astera Labs SEC filings","publisher":"Astera Labs, Inc.","url":"https://ir.asteralabs.com/financial-information/sec-filings","source_type":"regulatory_filing","retrieval_status":"search_result_only","content_inspected":false},{"title":"Credo PCIe and CXL retimer product line","publisher":"Credo Semiconductor","url":"https://credosemi.com/products/pcie/","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Merchant PCIe switch offerings from established suppliers","publisher":"Various","url":"https://www.broadcom.com/products/pcie-switches-bridges","source_type":"company_website","retrieval_status":"search_result_only","content_inspected":false},{"title":"Nvidia's Optical Boogeyman — NVL72, InfiniBand Scale Out, 800G & 1.6T Ramp","publisher":"SemiAnalysis","url":"https://newsletter.semianalysis.com/p/nvidias-optical-boogeyman-nvl72-infiniband","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"PCI-SIG PCIe 6.0 base specification","publisher":"PCI-SIG","url":"https://pcisig.com/specifications","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"Post describing a cableless Rubin midplane redesign","publisher":"X (formerly Twitter)","url":"https://x.com/TheValueist/status/1983276631348195593","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"UALink specification","publisher":"UALink Consortium","url":"https://ualinkconsortium.org/","source_type":"other","retrieval_status":"search_result_only","content_inspected":false}],"concepts":[{"slug":"ai-fabric-connectivity-silicon","name":"AI Fabric Connectivity Silicon","category":"component","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#ai-fabric-connectivity-silicon","assertions":[{"id":"652494ca-f2b7-435d-8a52-0cd8587debd0","predicate":"concept.description","statement":"The category widened from PCIe retimers to fabric switches, CXL memory controllers, 1.6T and 3.2T Ethernet signal conditioners, seven-metre cable modules and optical work — including a footprint-compatible family letting architects swap a redriver for a retimer without redesigning the board.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"53b38bb0-0e3f-4e3b-ae53-10f879387606","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"The Long & Short of AI: Building Scalable Data Centers in the PCIe 6 Era","publisher":"Astera Labs, Inc.","url":"https://www.asteralabs.com/the-long-and-short-of-ai-building-scalable-data-centers-in-the-pcie-6-x-era/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"2d3b843f-931b-4bfa-885a-69eed562de11","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Astera Labs Reports Second Quarter 2026 Financial Results","publisher":"Astera Labs, Inc.","url":"https://ir.asteralabs.com/news-releases/news-release-details/astera-labs-reports-second-quarter-2026-financial-results","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-08-04","documents":[]}}]},{"id":"7e8794ef-89ab-477e-a517-25bc682d2751","predicate":"concept.description","statement":"Astera Labs reported revenue of $392.4 million for the quarter ended 30 June 2026, up 104% year over year at a 73.3% GAAP gross margin and 22.7% operating margin, guiding to $540-560 million — margins that show what a hard-to-substitute connectivity component earns when what it enables is scarce.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"d92cfef0-d9ff-484f-9869-093c423832bc","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Astera Labs Reports Second Quarter 2026 Financial Results","publisher":"Astera Labs, Inc.","url":"https://ir.asteralabs.com/news-releases/news-release-details/astera-labs-reports-second-quarter-2026-financial-results","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-08-04","documents":[]}}]}]},{"slug":"ai-rack-power-density","name":"AI Rack Power Density","category":"component","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#ai-rack-power-density","assertions":[]},{"slug":"nvlink-scale-up-fabric","name":"NVLink and the Scale-Up Fabric","category":"interconnect","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#nvlink-scale-up-fabric","assertions":[]},{"slug":"scale-up-versus-scale-out","name":"Scale-Up Versus Scale-Out","category":"interconnect","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#scale-up-versus-scale-out","assertions":[]},{"slug":"copper-reach-limit","name":"The Copper Reach Limit","category":"interconnect","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#copper-reach-limit","assertions":[]},{"slug":"retimer","name":"The Retimer","category":"component","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#retimer","assertions":[{"id":"661a87c0-1663-4bb5-ac9b-5b259f05b6a8","predicate":"concept.description","statement":"Every technical account of retimers read for this collection was written by a company selling the part, including a trade-site page labelled a sponsor blog — so while two competitors corroborate the standards-set loss budgets, the inference that a system needs a retimer comes only from retimer vendors, and the specification itself was not read.","assessment":"unverified","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"709a292d-9f00-49a3-9a3d-d0b112769ae4","stance":"qualifies","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Using A Retimer To Extend Reach For PCIe 6.0 Designs","publisher":"Semiconductor Engineering (sponsored post by Rambus)","url":"https://semiengineering.com/using-a-retimer-to-extend-reach-for-pcie-6-0-designs/","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":"2023-08-10","documents":[]}}]},{"id":"edfce2c1-905f-4b8d-939d-af9fa28bfe70","predicate":"concept.description","statement":"Without a retimer, PCIe 6.0 board reach is stated at 4.3 inches on low-loss material and 7.1 inches on ultra-low-loss, against a specification assuming roughly 18 inches of trace; a retimer roughly doubles those to 9.9 and 15.1 inches by using clock data recovery to retransmit a fresh copy on a clean clock, resetting the jitter and loss budgets.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"5e2de34a-652f-40cb-87b1-4a269b96525d","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"The Long & Short of AI: Building Scalable Data Centers in the PCIe 6 Era","publisher":"Astera Labs, Inc.","url":"https://www.asteralabs.com/the-long-and-short-of-ai-building-scalable-data-centers-in-the-pcie-6-x-era/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"80a2c13e-a2fc-499f-80f6-f3b861b2a7fb","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"PCIe Retimers vs. Redrivers: Ensuring Signal Integrity for AI Infrastructure","publisher":"Astera Labs, Inc.","url":"https://www.asteralabs.com/pcie-retimers-vs-redrivers-ensuring-signal-integrity-for-ai-infrastructure/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]}]},{"slug":"signal-integrity-budget","name":"The Signal Integrity Budget","category":"interconnect","canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#signal-integrity-budget","assertions":[{"id":"511f3ed1-18fc-47e4-9b42-65ed543d13b5","predicate":"concept.description","statement":"PCIe 6.0 tightened the pad-to-pad loss budget to 32 dB from PCIe 5.0's 36 dB at a 16 GHz Nyquist frequency, while moving to PAM4 signalling that costs roughly 9 dB of signal-to-noise and about a third of the timing interval — against essentially unchanged trace-length targets of roughly 18 inches total.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"d4f1dfaa-8939-4cf8-8abe-f64a6352adf0","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"The Long & Short of AI: Building Scalable Data Centers in the PCIe 6 Era","publisher":"Astera Labs, Inc.","url":"https://www.asteralabs.com/the-long-and-short-of-ai-building-scalable-data-centers-in-the-pcie-6-x-era/","source_type":"company_website","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}},{"id":"8b3e4fc4-d0e7-483f-9566-22d21d4f1b14","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Using A Retimer To Extend Reach For PCIe 6.0 Designs","publisher":"Semiconductor Engineering (sponsored post by Rambus)","url":"https://semiengineering.com/using-a-retimer-to-extend-reach-for-pcie-6-0-designs/","source_type":"other","retrieval_status":"fetched","content_inspected":true,"published_at":"2023-08-10","documents":[]}}]}]}],"events":[{"slug":"astera-labs-q2-2026-results","title":"Fabric Switches Overtake Signal Conditioning","category":"other","event_date":"2026-08-04","date_precision":"day","country":"United States","region":null,"canonical_url":"https://www.manufacturing.ai/topics/connectivity-silicon#astera-labs-q2-2026-results","assertions":[{"id":"fb7101b4-0934-46c4-9963-728788049052","predicate":"event.description","statement":"Astera Labs reported preliminary revenue of $392.4 million for the quarter ended 30 June 2026, up 104% year over year at a 73.3% GAAP gross margin, guiding to $540-560 million, and stated that fabric switches would become its largest product family in the following quarter — a quarter earlier than expected.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"d942c3b5-c2ff-4180-abd9-bcfa5d45293f","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Astera Labs Reports Second Quarter 2026 Financial Results","publisher":"Astera Labs, Inc.","url":"https://ir.asteralabs.com/news-releases/news-release-details/astera-labs-reports-second-quarter-2026-financial-results","source_type":"press_release","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-08-04","documents":[]}}]}]}],"policy":{"publication_model":"transparency","evidence_entries_may_share_a_source":true,"linked_documents_do_not_add_verification":true,"correction_intake_available":false,"assessment_meanings":{"primary-source confirmed":"Editor-reviewed against a first-party source.","cross-source corroborated":"Editor-confirmed across two independent origins.","reported":"Supported by the attached sources; not yet editor-reviewed.","disputed":"Sources conflict; competing accounts are both attached.","superseded":"Replaced by a newer assertion.","unverified":"No supporting evidence attached."},"evidence_eligibility":"`evidence[]` contains only sources whose content was actually retrieved and read (`content_inspected: true`). Sources that could not be retrieved are counted per-assertion in `reference_only_source_count`, listed for the whole collection in `consulted_references`, and never presented as evidence. `source_count` counts only sources an assertion actually rests on — it deliberately excludes `consulted_references`, so it is never inflated by material nobody could read.","topic_scope":"Assertions and source counts are limited to the topic's current packet lineage. Reusing a concept in another topic does not silently import that other topic's assertions.","rights":"Statements are Manufacturing.ai's own prose. Source excerpts are not redistributed; `quote` is present only where explicitly cleared.","attribution":"Cite as Manufacturing.ai, https://www.manufacturing.ai/topics/connectivity-silicon","correction_url":"https://www.manufacturing.ai/methodology#corrections"}}