For most of the current AI build-out, the step that limited how many accelerators could be built was not lithography. It was packaging — the assembly of logic dies and memory stacks onto a shared substrate. TrendForce reported in June 2026 that the CoWoS supply-demand gap stood at around 20%, narrowing to about 10% by year end, with TSMC running 120,000 to 140,000 wafers a month and outsourced partners adding 50,000 to 60,000 more. Those figures come with a caution the report states itself: they are attributed to unnamed institutional investors via a newspaper, not to TSMC.
That a packaging number is the headline at all is the change worth understanding. TSMC puts it plainly on its own site: packaging technologies “were once considered simple backend processes, almost an inconvenience”, and are now “critical to a product’s performance, function, and cost”. Its 3DFabric family — SoIC, CoWoS and InFO — deliberately spans both wafer-level frontend and backend work, because the boundary between making a chip and packaging one has stopped being a boundary. The cheapest-subcontractor step became the most advanced foundry’s competitive advantage.
The next structural change is the shape of what the work is done on. A round wafer wastes area at its edges when the products cut from it are large rectangles, and accelerator packages are now large rectangles. Chip-on-Panel-on-Substrate moves onto a square panel: TSMC has standardised on 310 by 310 millimetres, with pilot production targeted for 2027, mass production in the second half of 2028, and glass core substrates after 2030. Taiwan panel makers already run fan-out panel-level packaging up to 620 by 750 millimetres for mature products, so the base exists; what is new is bringing leading-edge accelerator work onto it. Every one of those dates is a forecast.
Underneath the capacity story sits the design idea that created the demand. A chiplet is a die built to be combined with others rather than to work alone, and UCIe is the industry standard for connecting them across vendors — released in 2022 and revised through 2025. The reason this matters more each year is covered on the GPU page: once a design reaches the reticle limit, continuing means building from several dies, and the quality of the connection between them becomes as important as the arithmetic inside them.
What is missing is named rather than implied. TSMC’s SoIC page returned an error, so this collection cannot state bond pitches or interconnect densities — the numbers that would show concretely how much finer direct bonding is than microbumps, and the most useful thing a later pass could add. Intel’s advanced packaging page and a Semiconductor Engineering article both refused the fetcher, so nothing is asserted here about EMIB, Foveros or hybrid bonding. And several widely-circulated articles credit the panel-level move with lifting area utilisation past 90% and cutting cost 20 to 30%; those figures do not appear in the research this collection read, and are not repeated.