{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/advanced-packaging","topic":{"slug":"advanced-packaging","name":"How AI Compute Gets Built: Advanced Packaging","description":"A sourced reference collection on advanced semiconductor packaging — CoWoS, chiplets, and the UCIe interconnect standard — the capacity constraint that limited AI chip production more than logic fabrication did.","coverage_notes":"Second packet through the pipeline, rebuilt in September 2026 to the reference-collection template and reweighted toward current developments: the capacity constraint and the move to panel-level packaging now lead, with the UCIe standards history retained as background rather than as the spine. Fourteen sources were consulted: nine were retrieved and read, three were attempted and could not be read, and four were surfaced and set aside with a stated reason. Two of the reads are new and recent — TSMC's own 3DFabric page, obtained in a browser after an HTTP 403, and TrendForce's June 2026 report on CoPoS. One set-aside entry is unusual and deliberate: a widely-circulated article attributes to that TrendForce research a 30% cost reduction and 90%-plus utilisation figure which does not appear in it, and it is listed so a reader meeting those numbers elsewhere can see that this collection looked and could not substantiate them. Capacity figures throughout carry the attribution chain their source states — institutional investors via Economic Daily News, not TSMC. Named gaps: TSMC's SoIC page returns HTTP 404, so no bond pitch or interconnect density is asserted anywhere here; Intel's advanced-packaging page and a Semiconductor Engineering article both returned HTTP 403, so this collection still asserts nothing about EMIB, Foveros or hybrid bonding. The CoWoS, interposer and through-silicon-via concepts are shared with the HBM collection rather than duplicated. Not yet editor-reviewed; every assertion reads as reported.","primer":"For most of the current AI build-out, the step that limited how many accelerators could be built was not lithography. It was packaging — the assembly of logic dies and memory stacks onto a shared substrate. TrendForce reported in June 2026 that the CoWoS supply-demand gap stood at around 20%, narrowing to about 10% by year end, with TSMC running 120,000 to 140,000 wafers a month and outsourced partners adding 50,000 to 60,000 more. Those figures come with a caution the report states itself: they are attributed to unnamed institutional investors via a newspaper, not to TSMC.\n\nThat a packaging number is the headline at all is the change worth understanding. TSMC puts it plainly on its own site: packaging technologies “were once considered simple backend processes, almost an inconvenience”, and are now “critical to a product’s performance, function, and cost”. Its 3DFabric family — SoIC, CoWoS and InFO — deliberately spans both wafer-level frontend and backend work, because the boundary between making a chip and packaging one has stopped being a boundary. The cheapest-subcontractor step became the most advanced foundry’s competitive advantage.\n\nThe next structural change is the shape of what the work is done on. A round wafer wastes area at its edges when the products cut from it are large rectangles, and accelerator packages are now large rectangles. Chip-on-Panel-on-Substrate moves onto a square panel: TSMC has standardised on 310 by 310 millimetres, with pilot production targeted for 2027, mass production in the second half of 2028, and glass core substrates after 2030. Taiwan panel makers already run fan-out panel-level packaging up to 620 by 750 millimetres for mature products, so the base exists; what is new is bringing leading-edge accelerator work onto it. Every one of those dates is a forecast.\n\nUnderneath the capacity story sits the design idea that created the demand. A chiplet is a die built to be combined with others rather than to work alone, and UCIe is the industry standard for connecting them across vendors — released in 2022 and revised through 2025. The reason this matters more each year is covered on the GPU page: once a design reaches the reticle limit, continuing means building from several dies, and the quality of the connection between them becomes as important as the arithmetic inside them.\n\nWhat is missing is named rather than implied. TSMC’s SoIC page returned an error, so this collection cannot state bond pitches or interconnect densities — the numbers that would show concretely how much finer direct bonding is than microbumps, and the most useful thing a later pass could add. Intel’s advanced packaging page and a Semiconductor Engineering article both refused the fetcher, so nothing is asserted here about EMIB, Foveros or hybrid bonding. And several widely-circulated articles credit the panel-level move with lifting area utilisation past 90% and cutting cost 20 to 30%; those figures do not appear in the research this collection read, and are not repeated.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":8,"inspected_source_count":8,"consulted_reference_count":7,"blocked_reference_count":3,"set_aside_reference_count":4},"figures":[{"kind":"time-series","title":"Packaging capacity, and the gap it is closing","caption":"Reported monthly CoWoS wafer capacity in 2026. The industry total is the sum of the foundry and its outsourced partners.","sourceNote":"TrendForce, 15 June 2026. The report attributes these figures to unnamed institutional investors via Economic Daily News rather than to TSMC. Ranges are shown at their midpoints; all are estimates for a year in progress, not measured output.","unit":"CoWoS wafers per month, thousands","points":[{"label":"TSMC (120-140k)","value":130,"display":"~130k"},{"label":"OSAT partners (50-60k)","value":55,"display":"~55k"},{"label":"Industry total","value":185,"display":"~185k"}]}],"blocked_references":[{"title":"All AI Data Center Interconnects Will Be Optical Within 5 Years","publisher":"Semiconductor Engineering","url":"https://semiengineering.com/all-ai-data-center-interconnects-will-be-optical-within-5-years/","source_type":"journalism","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"Intel Foundry — Advanced Packaging (EMIB, Foveros)","publisher":"Intel","url":"https://www.intel.com/content/www/us/en/foundry/advanced-packaging.html","source_type":"company_website","retrieval_status":"blocked_403","content_inspected":false,"published_at":null},{"title":"TSMC-SoIC (expected location)","publisher":"TSMC","url":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/tsmc-soic.htm","source_type":"company_website","retrieval_status":"blocked_404","content_inspected":false,"published_at":null}],"set_aside_references":[{"title":"Chip-on-Wafer-on-Substrate (CoWoS) - TSMC","publisher":"WikiChip","url":"https://en.wikichip.org/wiki/tsmc/cowos","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"TSMC Accelerates CoPoS Packaging to Replace CoWoS, as Glass Core Substrates Cut Costs 30% and Boost Wafer Utilization Past 90%","publisher":"Wccftech","url":"https://wccftech.com/tsmc-accelerates-copos-packaging-replace-cowos-as-glass-core-substrates-cut-costs-boost-wafer-utilizatio/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"TSMC Advances Panel-Level Packaging, CoPoS Pilot Line Reportedly Set for June Completion","publisher":"TrendForce","url":"https://www.trendforce.com/news/2026/04/13/news-tsmc-advances-panel-level-packaging-copos-pilot-line-reportedly-set-for-june-completion-2028-29-ramp-eyed/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"TSMC Prepares CoPoS: Next-Gen 310 x 310 mm Packages","publisher":"TechPowerUp","url":"https://www.techpowerup.com/337960/tsmc-prepares-copos-next-gen-310-x-310-mm-packages","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false}],"concepts":[{"slug":"advanced-packaging","name":"Advanced Packaging","category":"packaging_technology","canonical_url":"https://www.manufacturing.ai/topics/advanced-packaging#advanced-packaging","assertions":[{"id":"4cf58897-1a1d-4714-88b4-f41e53a677f9","predicate":"concept.description","statement":"TSMC has publicly stated a CoWoS capacity CAGR above 80% for 2022-2027; the widely-cited 120,000-140,000 wafers-per-month figure for 2026 is an analyst estimate attributed to unnamed institutional investors, not a TSMC disclosure.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"e1fab199-ec6a-4dea-859d-9cf1087f0122","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026","publisher":"TrendForce","url":"https://www.trendforce.com/news/2026/06/15/news-tsmc-cowos-supply-demand-gap-reportedly-seen-narrowing-from-20-to-10-by-end-2026-as-capacity-expands/","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-06-15","documents":[]}},{"id":"6bb3001a-28ad-437b-8bf6-61284e470cc5","stance":"qualifies","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026","publisher":"TrendForce","url":"https://www.trendforce.com/news/2026/06/15/news-tsmc-cowos-supply-demand-gap-reportedly-seen-narrowing-from-20-to-10-by-end-2026-as-capacity-expands/","source_type":"journalism","retrieval_status":"fetched","content_inspected":true,"published_at":"2026-06-15","documents":[]}}]},{"id":"50588a4d-274f-4886-9dea-056fd82dffa5","predicate":"concept.description","statement":"Advanced packaging and HBM — not logic dies — were the binding constraint on AI chip production in 2025, with the four largest AI chip designers consuming ~90% of global CoWoS and HBM supply but only ~12% of advanced logic die production.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"269c7185-a65c-4a3c-9a2a-cf1b2cf20d36","stance":"supports","is_primary_for_assertion":false,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"Advanced packaging and HBM, not logic dies, were the bottlenecks on AI chip production in 2025","publisher":"Epoch AI","url":"https://epoch.ai/data-insights/ai-chip-supply-chain-constraints","source_type":"academic","retrieval_status":"fetched","content_inspected":true,"published_at":null,"documents":[]}}]},{"id":"d53836e5-d317-41dd-900f-2315c00de268","predicate":"concept.description","statement":"Advanced packaging integrates multiple separately-manufactured dies into one package with dense short interconnects; TSMC's CoWoS platform, which places an SoC and multiple HBM stacks on a shared interposer at over 2x reticle size, is the dominant implementation for AI accelerators.","assessment":"reported","editor_reviewed":false,"reference_only_source_count":0,"evidence":[{"id":"782de75e-0856-4109-8d21-65167630b6fc","stance":"supports","is_primary_for_assertion":true,"origin_independence":"unknown","note":null,"quote":null,"source":{"title":"CoWoS® Packaging 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