{"schema_version":"2026-09-05.topic-graph-v1","canonical_url":"https://www.manufacturing.ai/topics/gpu","topic":{"slug":"gpu","name":"GPUs and AI Accelerators: How the Chips That Train AI Are Designed, Made and Sold","description":"A sourced reference collection on the AI accelerator — what a GPU actually is and why it is fast, how the reticle limit forced it onto two dies, the four industries that have to deliver before one ships, what the money and the customer concentration look like in the filings, and how export control turned chip performance into a regulated quantity.","coverage_notes":"Fourth packet built to the reference-collection template rather than a news window, and the first covering the compute side of the AI supply chain. Sixty-five sources were consulted: twenty-eight were retrieved and read, three were attempted and could not be read, and thirty-four were surfaced and deliberately set aside with a stated reason each. The strongest material is regulatory — NVIDIA's fiscal 2026 annual report, TSMC's filed quarterly release, and the Federal Register texts of both the October 2022 advanced-computing rule and its October 2023 revision — all read through ordinary browser access to public pages after the automated fetcher was refused. Those two rule texts together correct a widely-repeated misstatement of the 2022 thresholds and show the control being rewritten around performance density once hardware had been designed against it. Vendor performance multiples are attributed to the vendor throughout and never treated as measurements; no market-share percentage is asserted anywhere, because no source read here states one with a traceable denominator. One retrieved figure — A100 memory bandwidth — was discarded as an evident misread and the omission is disclosed rather than papered over. Remaining named gaps: Rubin's per-GPU memory and compute figures, which NVIDIA has not published; AMD's per-GPU and aggregate Helios figures, which neither AMD document states; Intel's Gaudi 3 node, memory and bandwidth, likewise unpublished; and TSMC's revenue-by-platform split, which lives in an unretrieved slide deck. Geographically this collection reaches the United States, Taiwan, South Korea, Japan and China across twenty-seven years. Not yet editor-reviewed; every assertion reads as reported.","primer":"An AI accelerator is not a faster computer. It is a computer that spent its transistors differently. NVIDIA's own documentation puts the bargain plainly: a GPU is “designed such that more transistors are devoted to data processing rather than data caching and flow control”. A CPU spends its area on caches and control logic so one chain of dependent instructions runs as quickly as possible; a GPU spends the same area on arithmetic units and covers memory latency by keeping enough independent work queued. That is the whole reason the same part is extraordinary at training a neural network and unremarkable at running an operating system.\n\nThe category was named on 11 October 1999, when NVIDIA launched the GeForce 256 — 17 million transistors on a TSMC 220 nm process — and defined a GPU as a single-chip processor with integrated transform, lighting, triangle setup and rendering engines handling at least 10 million polygons per second. Its real innovation was moving geometry work off the CPU. In November 2006 CUDA made that parallel engine addressable in a general-purpose language instead of only through the graphics pipeline. Then in 2012 a paper by Krizhevsky, Sutskever and Hinton reported ImageNet top-5 error of 18.9% from a 60-million-parameter network, crediting “a very efficient GPU implementation” for making the training tractable. Six years of available capability, and then a demand curve that has not stopped.\n\nThe hardware answered by dedicating silicon to one operation. The V100 of May 2017 introduced tensor cores, which multiply two 4x4 FP16 matrices and add a third — the inner loop of essentially all deep learning. Every generation since has changed the precision rather than the operation: TensorFloat-32 and bfloat16 with the A100 in 2020, an FP8 transformer engine with the H100 in 2022, 4-bit floating point with Blackwell in 2024. FP8 became usable across vendors because NVIDIA, Arm and Intel published a shared format in September 2022 — E4M3 for weights and activations, E5M2 for gradients — rather than each inventing their own.\n\nThen physics intervened. A lithography scanner can only project so large an image in one exposure: 26 mm by 33 mm at the 0.33 numerical aperture of current EUV tools, and 26 mm by 16.5 mm at high-NA, because those optics are anamorphic. NVIDIA's die area sat between 610 and 826 square millimetres across the P100, V100, A100 and H100 while transistor count rose from 15.3 to 80 billion — all of the growth came from process density, against a wall the area could not cross. Blackwell went around it: 208 billion transistors as two reticle-limited dies joined by a 10 TB/s link and presented as one GPU. At that point accelerator design stops being a logic problem and becomes a packaging problem.\n\nNobody makes one of these alone. NVIDIA states in its annual report that it uses “a fabless and contracting manufacturing strategy” covering wafer fabrication, assembly, testing and packaging, and names the suppliers: wafers from TSMC and Samsung, memory from SK hynix, Micron and Samsung, CoWoS for packaging, and Hon Hai, Wistron and Fabrinet for assembly and test. In the quarter ended 30 June 2026 TSMC reported that 77% of its wafer revenue came from 7-nanometer and below. The coupling is tight enough to be visible in the calendar: on 16 March 2026 NVIDIA announced the Vera Rubin platform and Micron announced volume production of HBM4 built for it — the same day, because the accelerator generation and the memory generation are specified and qualified together.\n\nThe money is concentrated at both ends. NVIDIA's fiscal 2026, ended 25 January 2026, produced $215.9 billion of revenue against $60.9 billion two years earlier, with $193.7 billion of it from Data Center and $120.1 billion of net income — from a company that owns no factory. In the same year one direct customer was 22% of total revenue and another was 14%. Three memory makers and one leading foundry at one end; a handful of buyers at the other. The two quarters since have run $81.6 billion and $96.2 billion, with guidance of $108.0 billion issued on 26 August 2026 — a projection, not a result.\n\nCompetition now comes from two directions at once. AMD launched the Instinct MI400 series on 23 July 2026, competing at rack scale rather than by the card. And the largest buyers are building their own: Google documents its seventh-generation TPU at 192 GiB of HBM per chip and pods of 9,216 chips, and Amazon announced Trainium3 in December 2025 as its first 3-nanometer part. TrendForce projected in January 2026 that ASIC-based AI servers would reach nearly 28% of shipments against 69.7% for GPU-based systems — a forecast published before the year it describes, and treated here as one.\n\nSince 7 October 2022 the performance of these chips has been a regulated quantity. The US rule creating ECCN 3A090 controls circuits that combine 600 GByte/s of aggregate input-output with a bit-length-times-TOPS product of 4,800 or more, naming GPUs, TPUs and neural processors as in scope. What that costs is on the record: an April 2025 licence requirement for the H20 produced a $4.5 billion charge, later licences yielded about $60 million of revenue, and by August 2026 NVIDIA's own guidance assumed no Data Center compute revenue from China at all.\n\nWhat is missing is stated beside the claims rather than hidden. NVIDIA has not published per-GPU HBM4 capacity, bandwidth or FP4 throughput for Rubin, and the figures circulating for those come from resellers and conference coverage, so none is recorded here. AMD gives a rack total of 3 AI exaflops but still no HBM4 capacity, aggregate bandwidth or precision split. Intel publishes no node, memory or bandwidth for Gaudi 3. TSMC's revenue-by-platform split lives in a slide deck that could not be retrieved. One report places the Vera Rubin full-production announcement at a CES keynote rather than the March newsroom post, and that discrepancy is published rather than resolved. And the widely-quoted claim that NVIDIA holds 70, 80 or 92 percent of this market is asserted nowhere here, because no source read for this collection states one with a denominator you could check.","primer_note":"Manufacturing.ai's own editorial synthesis, not evidence. Every factual statement in it is separately asserted and sourced in this response's concepts and events.","reviewed_through_date":null,"source_count":28,"inspected_source_count":28,"consulted_reference_count":40,"blocked_reference_count":3,"set_aside_reference_count":37},"figures":[{"kind":"time-series","title":"Three fiscal years","caption":"NVIDIA's total revenue as reported in its annual report. The company owns no factory; this is what a design plus a purchase order was worth.","sourceNote":"NVIDIA Form 10-K for the fiscal year ended 25 January 2026, filed 25 February 2026. All three figures are reported results from the same filing's comparative tables, not projections.","unit":"Revenue, billions of US dollars","points":[{"label":"FY2024","value":60.922,"display":"$60.9bn"},{"label":"FY2025","value":130.497,"display":"$130.5bn"},{"label":"FY2026","value":215.938,"display":"$215.9bn"}]},{"kind":"composition","title":"What the revenue actually is","caption":"NVIDIA's fiscal 2026 revenue by end market. Data centre compute alone is three quarters of the company; gaming, the business the company was built on, is 7%.","sourceNote":"NVIDIA Form 10-K for the fiscal year ended 25 January 2026. Reported figures using NVIDIA's own end-market definitions, from the revenue-by-specialized-markets table.","totalDisplay":"$215.9bn","parts":[{"label":"Data Center — compute","value":162.361,"display":"$162.4bn"},{"label":"Data Center — networking","value":31.376,"display":"$31.4bn"},{"label":"Gaming","value":16.042,"display":"$16.0bn"},{"label":"Professional Visualization","value":3.191,"display":"$3.2bn"},{"label":"Automotive","value":2.349,"display":"$2.3bn"},{"label":"OEM and other","value":0.619,"display":"$0.6bn"}]},{"kind":"time-series","title":"Two quarters and a projection","caption":"The most recent reported quarters, and the guidance issued alongside the second. The third column has not happened.","sourceNote":"NVIDIA quarterly results releases of 20 May 2026 and 26 August 2026. The first two columns are reported results; the third is NVIDIA's own guidance of $108.0bn plus or minus 2%, issued 26 August 2026 and stated to assume no Data Center compute revenue from China.","unit":"Revenue, billions of US dollars","points":[{"label":"FQ1-27","value":81.6,"display":"$81.6bn"},{"label":"FQ2-27","value":96.2,"display":"$96.2bn"},{"label":"FQ3-27 guide","value":108,"display":"$108.0bn"}]},{"kind":"time-series","title":"The die that stopped growing","caption":"Four generations of NVIDIA data-centre silicon. Area flattens against the reticle limit after 2017 while transistor count rises from 15.3 to 80 billion — and then the next generation needed two dies.","sourceNote":"Die areas from the Wikipedia articles on the Pascal, Volta, Ampere and Hopper microarchitectures, each read directly. Tertiary sources, reporting manufacturer specifications; measured die areas, not projections.","unit":"Die area, square millimetres","points":[{"label":"GP100 (2016)","value":610,"display":"610 mm²"},{"label":"GV100 (2017)","value":815,"display":"815 mm²"},{"label":"GA100 (2020)","value":826,"display":"826 mm²"},{"label":"GH100 (2022)","value":814,"display":"814 mm²"}]},{"kind":"composition","title":"Where the leading foundry's wafers go","caption":"TSMC's wafer revenue by process node in the quarter ended 30 June 2026. Nodes that barely existed five years ago are 77% of it.","sourceNote":"TSMC second-quarter 2026 earnings release, filed with the SEC on 16 July 2026. Reported percentages of total wafer revenue. The release states these figures had not been approved by the board of directors when published. The 'Older than 7nm' share is the remainder of the disclosed mix.","totalDisplay":"100% of wafer revenue","parts":[{"label":"2 nm","value":3,"display":"3%"},{"label":"3 nm","value":30,"display":"30%"},{"label":"5 nm","value":33,"display":"33%"},{"label":"7 nm","value":11,"display":"11%"},{"label":"Older than 7 nm","value":23,"display":"23%"}]},{"kind":"share-comparison","title":"The buyers moved home","caption":"Share of NVIDIA's revenue by the headquarters location of its direct customers. In two fiscal years the non-US share fell from nearly half to under a third.","sourceNote":"NVIDIA Form 10-K for the fiscal year ended 25 January 2026. The filing discloses the share from customers headquartered outside the United States (48%, 41%, 31%); the United States series is its complement. Revenue is attributed to a direct customer's headquarters, which the filing warns is not where the equipment ends up.","points":["FY2024","FY2025","FY2026"],"seriesA":{"label":"Customers headquartered in the United States","values":[52,59,69]},"seriesB":{"label":"Customers headquartered elsewhere","values":[48,41,31]},"gapLabel":"The gap opens from 4 to 38 percentage points in two years."}],"blocked_references":[{"title":"NVIDIA Corporation, Annual Report on Form 10-K, fiscal year 2025 (investor-relations PDF)","publisher":"NVIDIA","url":"https://s201.q4cdn.com/141608511/files/doc_financials/2025/q4/177440d5-3b32-4185-8cc8-95500a9dc783.pdf","source_type":"regulatory_filing","retrieval_status":"retrieved_no_content","content_inspected":false,"published_at":null},{"title":"NVIDIA Vera Rubin platform product page (expected location)","publisher":"NVIDIA","url":"https://www.nvidia.com/en-us/data-center/vera-rubin/","source_type":"company_website","retrieval_status":"blocked_404","content_inspected":false,"published_at":null},{"title":"TSMC Quarterly Results, second quarter 2026 (investor relations)","publisher":"TSMC","url":"https://investor.tsmc.com/english/quarterly-results/2026/q2","source_type":"company_website","retrieval_status":"retrieved_no_content","content_inspected":false,"published_at":null}],"set_aside_references":[{"title":"AI Accelerator Chips Market Size & Share, Industry Report","publisher":"Global Market Insights","url":"https://www.gminsights.com/industry-analysis/ai-accelerator-chips-market","source_type":"other","retrieval_status":"search_result_only","content_inspected":false},{"title":"AMD touts Instinct MI430X, MI440X, and MI455X AI accelerators and Helios rack-scale AI architecture at CES","publisher":"Tom’s Hardware","url":"https://www.tomshardware.com/tech-industry/artificial-intelligence/amd-touts-instinct-mi430x-mi440x-and-mi455x-ai-accelerators-and-helios-rack-scale-ai-architecture-at-ces-full-mi400-series-family-fulfills-a-broad-range-of-infrastructure-and-customer-requirements","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"AMD unveils full MI400 product lineup, claims MI500 chips will deliver 1,000x increase","publisher":"DataCenterDynamics","url":"https://www.datacenterdynamics.com/en/news/amd-unveils-full-mi400-product-lineup-claims-mi500-chips-will-deliver-1000x-increase-in-ai-performance/","source_type":"journalism","retrieval_status":"search_result_only","content_inspected":false},{"title":"ASIC Set to Outpace GPU? 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